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RamR

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Jun 27th, 2018
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_arith.all;
  4.  
  5. entity ramR is
  6. generic(
  7.     address_length: natural := 1
  8. );
  9. port(
  10.     clk: in std_logic;
  11.     rw_enable: in std_logic;
  12.     mem_enable: in std_logic;
  13.     address: in std_logic_vector((address_length - 1) downto 0);
  14.     data_input: in std_logic;
  15.     data_output: out std_logic
  16. );
  17. end ramR;
  18.  
  19. architecture arch of ramR is
  20.     type ram_type is array (0 to (2**(address_length) -1)) of std_logic;
  21.     signal ram: ram_type;
  22.     signal temp_address: std_logic_vector((address_length - 1) downto 0);
  23. begin
  24.  
  25. process(clk) is
  26. begin
  27.     if rising_edge(clk)and mem_enable = '1' then
  28.         if(rw_enable = '0') then
  29.             temp_address <= address;
  30.         elsif (rw_enable = '1') then
  31.             ram(conv_integer(unsigned(address))) <= data_input;
  32.         end if;
  33.     end if;
  34.    
  35. end process;
  36.  
  37. data_output <= ram(conv_integer(unsigned(temp_address)));
  38.  
  39. end arch;
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