20141002_KUAS_Verilog_FullAdder_8Bit(GateLevel)

/************************************************/
/** 20141002 8-Bit Full Adder (Use Gate Level) **/
/** Maker  : Yan                               **/
/** E-Mail : [email protected]             **/
/** Date   : 2014/10/02 pm.10:30               **/
/************************************************/

module FullAdder_8Bit(input1, input2, carryIn, sum, carryOut);
    input       [7:0]   input1, input2; input   carryIn;
    output      [7:0]   sum;        output  carryOut;
    wire        [6:0]   _wire;

    FullAdder   tmp1(.input1(input1[0]), .input2(input2[0]), .carryIn(carryIn), .sum(sum[0]), .carryOut(_wire[0]));
    FullAdder   tmp2(.input1(input1[1]), .input2(input2[1]), .carryIn(_wire[0]), .sum(sum[1]), .carryOut(_wire[1]));
    FullAdder   tmp3(.input1(input1[2]), .input2(input2[2]), .carryIn(_wire[1]), .sum(sum[2]), .carryOut(_wire[2]));
    FullAdder   tmp4(.input1(input1[3]), .input2(input2[3]), .carryIn(_wire[2]), .sum(sum[3]), .carryOut(_wire[3]));
    FullAdder   tmp5(.input1(input1[4]), .input2(input2[4]), .carryIn(_wire[3]), .sum(sum[4]), .carryOut(_wire[4]));
    FullAdder   tmp6(.input1(input1[5]), .input2(input2[5]), .carryIn(_wire[4]), .sum(sum[5]), .carryOut(_wire[5]));
    FullAdder   tmp7(.input1(input1[6]), .input2(input2[6]), .carryIn(_wire[5]), .sum(sum[6]), .carryOut(_wire[6]));
    FullAdder   tmp8(.input1(input1[7]), .input2(input2[7]), .carryIn(_wire[6]), .sum(sum[7]), .carryOut(carryOut));
endmodule

module FullAdder(input1, input2, carryIn, sum, carryOut);
    input       input1, input2, carryIn;
    output      sum, carryOut;
    wire        w1, w2, w3;

    HalfAdder   tmp1(.input1(input1), .input2(input2), .sum(w1), .carryOut(w2));
    HalfAdder   tmp2(.input1(w1), .input2(carryIn), .sum(sum), .carryOut(w3));

    or      (carryOut, w2, w3);
endmodule

module HalfAdder(input1, input2, sum, carryOut);
    input       input1, input2;
    output      sum, carryOut;

    xor     (sum, input1, input2);
    and     (carryOut, input1, input2);
endmodule