P04_NAND

-- Imagine you’re designing a smart lock system for a door. The door should remain locked (output HIGH = 1) unless two conditions are
-- met at the same time:
-- Condition A: Fingerprint
-- Condition B: Badge Scanned

library ieee;
use ieee.std_logic_1164.all;

entity SmartLock_TB is
end entity;

architecture Testbench of SmartLock_TB is
    signal Fingerprint, Badge, DoorLock : std_logic; -- Inputs and output
begin
    -- Instantiate the SmartLock design
    UUT: entity work.SmartLock
        port map (
            Fingerprint => Fingerprint,
            Badge       => Badge,
            DoorLock    => DoorLock
        );

    -- Testbench process
    process
    begin
        -- Test Case 1: No fingerprint, no badge
        Fingerprint <= '0';
        Badge <= '0';
        wait for 10 ns;

        -- Test Case 2: No fingerprint, badge scanned
        Fingerprint <= '0';
        Badge <= '1';
        wait for 10 ns;

        -- Test Case 3: Fingerprint present, no badge
        Fingerprint <= '1';
        Badge <= '0';
        wait for 10 ns;

        -- Test Case 4: Fingerprint and badge scanned
        Fingerprint <= '1';
        Badge <= '1';
        wait for 10 ns;

        wait; -- End simulation
    end process;
end architecture;