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Stage 1 (faulty ?) loader

ISSOtm Jan 5th, 2018 67 Never
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  1.  
  2. SECTION "Init vector", ROM0[$100]
  3.  
  4. InitVect::
  5.     di
  6.     jr Start
  7.     nop
  8.    
  9.     ds $150 - $104
  10.    
  11. Start::
  12.     cp $11
  13.     jr nz, Start ; Lock-up if not CGB
  14.    
  15.     ; Ensure we're in VBlank
  16. .waitVBlank
  17.     ldh a, [$FF44] ; LY
  18.     cp $90
  19.     jr nz, .waitVBlank
  20.    
  21.     ld hl, $8000
  22.     ld c, $10
  23.     xor a
  24. .clearTile0
  25.     ld [hli], a
  26.     dec c
  27.     jr nz, .clearTile0
  28.    
  29.     ld hl, $9800
  30.     ; xor a
  31.     ld [hl], a
  32.     inc a ; ld a, 1
  33.     ; Load VRAM bank 1
  34.     ld [$FF4F], a ; VBK
  35.     ld [hl], 0
  36.    
  37.     ld a, $80
  38.     ld c, $68
  39.     ld [c], a ; BGPI
  40.     inc c
  41.     add a, a
  42.     ld [c], a ; BGPD
  43.     ld [c], a ; BGPD
  44.    
  45.    
  46.     ld c, $51
  47.     ; Init HDMA src, just in case... doesn't matter, though
  48.     xor a
  49.     ld [c], a ; HDMA1
  50.     inc c
  51.     ld [c], a ; HDMA2
  52.     inc c
  53.     ; Init HDMA dest to end of VRAM bank 1
  54.     ld a, $1F
  55.     ld [c], a ; HDMA3
  56.     inc c
  57.     ld a, $F0
  58.     ld [c], a ; HDMA4
  59.    
  60.     ld b, (($20 + $B0 + $110) / $10 - 1) | $80
  61.     rst $00 ; DoHDMA
  62.    
  63.    
  64.     ld a, $0A
  65.     ld [$0000], a ; SRAMEnable
  66.     ld d, $00
  67.     xor a
  68. .copySRAM
  69.     ; Assume a == d
  70.     ld [$4000], a ; SRAMBank
  71.    
  72.     ld a, $A0
  73.     ld [$FF51], a ; HDMA1
  74.     xor a
  75.     ld [$FF52], a ; HDMA2
  76.    
  77.     ld b, $FF
  78.     rst $00 ; HDMA one half of SRAM over itself
  79.     rst $00 ; ...same
  80.    
  81.     inc d
  82.     ld a, d
  83.     cp 4
  84.     jr nz, .copySRAM
  85.    
  86.    
  87.     ; Fill a WRAM buffer with $FF for next HDMA
  88.     ld hl, $C000
  89.     ld bc, $330
  90. .fillBuf
  91.     ld a, $FF
  92.     ld [hli], a
  93.     dec bc
  94.     ld a, b
  95.     or c
  96.     jr nz, .fillBuf
  97.    
  98.     ld a, $C0
  99.     ld [$FF51], a ; HDMA1
  100.     xor a
  101.     ld [$FF52], a ; HDMA2
  102.     ld b, ($33 - 1) | $80
  103.     rst $00 ; HDMA over a buffer holding masks for the registers
  104.    
  105.    
  106.     ld c, $68
  107.     ld a, $80
  108.     ld [c], a ; BGPI
  109.     inc c
  110. .waitPaletteWrite1
  111.     ld a, [$FF41] ; STAT
  112.     and 2
  113.     jr nz, .waitPaletteWrite1
  114.     ; Set blue component of BG to 0x1F to signal Stage 2 completion
  115.     ld a, $1F
  116.     ld [c], a
  117.    
  118.    
  119.     ; Enter Stage 2
  120.    
  121.     ld c, $51
  122.     ld a, HIGH(Stage2Payload)
  123.     ld [c], a ; HDMA1
  124.     inc c
  125.     ld a, LOW(Stage2Payload)
  126.     ld [c], a ; HDMA2
  127.     inc c
  128.     ld a, $AC
  129.     ld [c], a ; HDMA3
  130.     inc c
  131.     ld a, $10
  132.     ld [c], a ; HDMA4
  133.     ld b, $80
  134.     rst $00
  135.    
  136.    
  137. .waitPaletteWrite2
  138.     ld a, [$FF41] ; STAT
  139.     and 2
  140.     jr nz, .waitPaletteWrite2
  141.     ; Set red component of BG to $1F to signal Stage 2 completion
  142.     ld a, $1F << 2
  143.     ld [$FF69], a ; BGPD
  144.    
  145.    
  146.     ; Lock up, wait for user to touch bottom screen
  147.    
  148.     jr @
  149.    
  150.    
  151.    
  152. SECTION "Do HDMA rst", ROM0[$000]
  153.  
  154. DoHDMA::
  155.     ld c, $41
  156.    
  157. .waitHBlank
  158.     ld a, [c] ; STAT
  159.     and 3
  160.     jr nz, .waitHBlank
  161.    
  162. .waitNotHBlank
  163.     ld a, [c] ; STAT
  164.     and 3
  165.     jr z, .waitNotHBlank
  166.    
  167.     ld c, $55
  168.     ld a, b
  169.     ld [c], a ; HDMA5
  170.    
  171. .waitHDMAEnd
  172.     ld a, [c] ; HDMA5
  173.     add a, a
  174.     jr nc, .waitHDMAEnd
  175.    
  176.     ret
  177.    
  178.     ; Also eats up rst 08 and rst 10
  179.    
  180.    
  181.    
  182. SECTION "Stage 2 payload", ROM0
  183.  
  184. Stage2Payload::
  185.     db $bc, $43, $94, $08, $41, $41, $41, $41
  186.    
  187.    
  188. SECTION "Ensure 1MB ROM", ROMX,BANK[$3F]
  189.     db 0
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