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- /* P940 board_p940.c by wkpark at gmail.com */
- #include <aboot/aboot.h>
- #include <aboot/io.h>
- #include <omap4/mux.h>
- #include <omap4/hw.h>
- #include <omap4/omap4_rom.h>
- #include <omap4/smc.h>
- #if 0
- #define PL310_POR 5
- #define PPA_SERVICE_PL310_POR 0x23
- #define PUBLIC_API_SEC_ENTRY 0x00
- typedef u32 (** const PUBLIC_SEC_ENTRY_Pub2SecDispatcher_pt) \
- (u32 appl_id, u32 proc_ID, u32 flag, ...);
- #define omap_smc_ppa \
- (*(PUBLIC_SEC_ENTRY_Pub2SecDispatcher_pt) \
- (PUBLIC_API_BASE_4430+PUBLIC_API_SEC_ENTRY))
- #define IVA_LDOSRAM_VOLTAGE_CTRL 0x4A002320
- #define MPU_LDOSRAM_VOLTAGE_CTRL 0x4A002324
- #define CORE_LDOSRAM_VOLTAGE_CTRL 0x4A002328
- #define SYSCTRL_PADCONF_CORE_EFUSE_1 0x4A100700
- #define SYSCTRL_PADCONF_CORE_EFUSE_2 0x4A100704
- u32 get_device_type(void)
- {
- /*
- * Retrieve the device type: GP/EMU/HS/TST stored in
- * CONTROL_STATUS
- */
- return (readl(CONTROL_STATUS) & DEVICE_MASK) >> 8;
- }
- #endif
- void board_late_init(void)
- {
- unsigned int rev = get_omap_rev();
- cfg_machine_type = 5001;
- if (rev != OMAP4430_ES1_0) {
- if (readl(0x4805D138) & (1<<22)) {
- /* enable software ioreq */
- sr32(0x4A30a31C, 8, 1, 0x1);
- /* set for sys_clk (38.4MHz) */
- sr32(0x4A30a31C, 1, 2, 0x0);
- /* set divisor to 2 */
- sr32(0x4A30a31C, 16, 4, 0x1);
- /* set the clock source to active */
- sr32(0x4A30a110, 0, 1, 0x1);
- /* enable clocks */
- sr32(0x4A30a110, 2, 2, 0x3);
- } else {
- /* enable software ioreq */
- sr32(0x4A30a314, 8, 1, 0x1);
- /* set for PER_DPLL */
- sr32(0x4A30a314, 1, 2, 0x2);
- /* set divisor to 16 */
- sr32(0x4A30a314, 16, 4, 0xf);
- /* set the clock source to active */
- sr32(0x4A30a110, 0, 1, 0x1);
- /* enable clocks */
- sr32(0x4A30a110, 2, 2, 0x3);
- }
- }
- #if 0
- if (rev > OMAP4430_ES1_0 && get_device_type() != GP_DEVICE) {
- /* Set PL310 Prefetch Offset Register w/PPA svc*/
- omap_smc_ppa(PPA_SERVICE_PL310_POR, 0, 0x7, 1, PL310_POR);
- /* Enable L2 data prefetch */
- omap_smc_rom(ROM_SERVICE_PL310_AUXCR_SVC,
- readl(OMAP44XX_PL310_AUX_CTRL) | 0x10000000);
- } else if (rev > OMAP4430_ES2_1) {
- /* Set PL310 Prefetch Offset Register using ROM svc */
- omap_smc_rom(ROM_SERVICE_PL310_POR_SVC, PL310_POR);
- /* Enable L2 data prefetch */
- omap_smc_rom(ROM_SERVICE_PL310_AUXCR_SVC,
- readl(OMAP44XX_PL310_AUX_CTRL) | 0x10000000);
- }
- #endif
- #if 0
- /* For ES2.2
- * 1. If unit does not have SLDO trim, set override
- * and force max multiplication factor to ensure
- * proper SLDO voltage at low OPP's
- * 2. Trim VDAC value for TV out as recomended to avoid
- * potential instabilities at low OPP's
- * 3.For all ESx.y trimmed and untrimmed units
- * Override efuse with LPDDR P:16/N:16 and
- * smart IO P:0/N:0 as per recomendation
- */
- // LGE_START 20110514++ need to check
- //writel(0x00084000, SYSCTRL_PADCONF_CORE_EFUSE_2);
- // LGE_END 20110514--
- if (rev >= OMAP4430_ES2_2) {
- /*if MPU_VOLTAGE_CTRL is 0x0 unit is not trimmed*/
- if (!readl(IVA_LDOSRAM_VOLTAGE_CTRL)) {
- /* Set M factor to max (2.7) */
- writel(0x0401040f, IVA_LDOSRAM_VOLTAGE_CTRL);
- writel(0x0401040f, MPU_LDOSRAM_VOLTAGE_CTRL);
- writel(0x0401040f, CORE_LDOSRAM_VOLTAGE_CTRL);
- // LGE_START 20110514++ need to check
- //writel(0x000001c0, SYSCTRL_PADCONF_CORE_EFUSE_1);
- // LGE_END 20110514--
- }
- }
- #endif
- }
- void board_mux_init(void)
- {
- /* from board_tuna.c and the disassembled x-load.bin of the SU540 */
- MV(CP(UART4_RX), (IEN | PTU | M0)); /* uart4_rx */
- MV(CP(UART4_TX), (M0)); /* uart4_tx */
- MV(CP(GPMC_NOE), (PTU | IEN | OFF_EN | M1)); /* sdmmc2_clk */
- MV(CP(GPMC_NWE), (PTU | IEN | OFF_EN | OFF_PU | OFF_IN | M1)); /* sdmmc2_cmd */
- MV(CP(GPMC_AD0), (PTU | IEN | OFF_EN | OFF_PU | OFF_IN | M1)); /* sdmmc2_dat0 */
- MV(CP(GPMC_AD1), (PTU | IEN | OFF_EN | OFF_PU | OFF_IN | M1)); /* sdmmc2_dat1 */
- MV(CP(GPMC_AD2), (PTU | IEN | OFF_EN | OFF_PU | OFF_IN | M1)); /* sdmmc2_dat2 */
- MV(CP(GPMC_AD3), (PTU | IEN | OFF_EN | OFF_PU | OFF_IN | M1)); /* sdmmc2_dat3 */
- MV(CP(GPMC_AD4), (PTU | IEN | OFF_EN | OFF_PU | OFF_IN | M1)); /* sdmmc2_dat4 */
- MV(CP(GPMC_AD5), (PTU | IEN | OFF_EN | OFF_PU | OFF_IN | M1)); /* sdmmc2_dat5 */
- MV(CP(GPMC_AD6), (PTU | IEN | OFF_EN | OFF_PU | OFF_IN | M1)); /* sdmmc2_dat6 */
- MV(CP(GPMC_AD7), (PTU | IEN | OFF_EN | OFF_PU | OFF_IN | M1)); /* sdmmc2_dat7 */
- }
- const struct ddr_regs ddr_regs_533mhz_2cs = {
- /* obtained by them devmem2 */
- .tim1 = 0x10EB0661, /* x-loader verified */
- .tim2 = 0x20370DD2,
- .tim3 = 0x00B1C33F,
- .phy_ctrl_1 = 0x049FF409, /* x-loader verified */
- .ref_ctrl = 0x00000618,
- #if defined(CONFIG_DDR_512MB)
- .config_init = 0x80000eb1,
- .config_final = 0x80001ab1,
- #else
- .config_init = 0x80000eb2,
- .config_final = 0x80001ab2,
- #endif
- .zq_config = 0x500B3214,
- .mr1 = 0x83,
- .mr2 = 0x4,
- };
- void board_ddr_init(void)
- {
- writel(0x80640300, DMM_BASE + DMM_LISA_MAP_0); // x-loader confirmed 07/19
- writel(0x00000000, DMM_BASE + DMM_LISA_MAP_2); // x-loader confirmed
- writel(0xFF020100, DMM_BASE + DMM_LISA_MAP_3); // x-loader confirmed
- writel(0x7c7c7c7c, 0x4A100638); /* obtained from the devmen2 */
- writel(0x7c7c7c7c, 0x4A10063c);
- writel(0x7c7c7c7c, 0x4A100640);
- writel(0x7c7c7c7c, 0x4A100648);
- writel(0x7c7c7c7c, 0x4A10064c);
- writel(0x7c7c7c7c, 0x4A100650);
- writel(0xa388bc03, 0x4A100644);
- writel(0xa388bc03, 0x4A100654);
- omap4_ddr_init(&ddr_regs_533mhz_2cs,
- &ddr_regs_533mhz_2cs);
- writel(0x0, 0x80000000); // x-loader confirmed
- writel(0x0, 0x80000080); // x-loader confirmed
- }
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