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  1. LIBRARY IEEE;
  2. USE IEEE.std_logic_1164.ALL;
  3. USE IEEE.numeric_std.ALL;
  4.  
  5. ENTITY rs232_tx IS
  6.   PORT(clk: IN std_logic;
  7.        tx: OUT std_logic;
  8.        rst: IN std_logic;
  9.        fifo_empty: IN std_logic;
  10.        fifo_RdEn, fifo_RdClock: OUT std_logic;
  11.        fifo_data: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
  12.        Q: OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
  13. END rs232_tx;
  14.  
  15. ARCHITECTURE working OF rs232_tx IS
  16.   TYPE state IS (idle,start,data);
  17.   SIGNAL tx_pulse: STD_LOGIC := '1';
  18.   SIGNAL s_tick: STD_LOGIC;
  19.   SIGNAL pr_state, nx_state: state := idle;
  20.   SIGNAL data_val: std_logic_vector(7 DOWNTO 0):=(others=>'0');
  21.   SIGNAL data_count: unsigned(2 DOWNTO 0):=to_unsigned(0,3);
  22. BEGIN
  23.   process(s_tick, rst)
  24.     VARIABLE count: unsigned(3 DOWNTO 0):= to_unsigned(0,4);
  25.   BEGIN
  26.     IF rising_edge(s_tick) THEN
  27.       count := count + to_unsigned(1,4);
  28.  
  29.       IF count = to_unsigned(15,4) THEN
  30.         tx_pulse <= '1';
  31.       ELSE
  32.         tx_pulse <='0';
  33.       END IF;
  34.     END IF;
  35.   END PROCESS;
  36.  
  37.   process(tx_pulse,rst)
  38.   BEGIN
  39.     IF rising_edge(tx_pulse) THEN
  40.       IF rst='1' THEN
  41.         pr_state <= idle;
  42.         data_val <= (others=>'0');
  43.         data_count <= to_unsigned(0,3);
  44.       ELSE
  45.         pr_state <= nx_state;
  46.         CASE pr_state IS
  47.           WHEN idle =>
  48.             data_count <= to_unsigned(0,3);
  49.           WHEN data =>
  50.             data_count <= data_count + to_unsigned(1,3);
  51.           WHEN start =>
  52.             data_val <= fifo_data;
  53.           WHEN OTHERS =>
  54.         END case;
  55.        
  56.       END IF;
  57.     END IF;
  58.   END process;
  59.  
  60.   process(fifo_empty,rst,data_count,pr_state,data_count)
  61.   BEGIN
  62.     case pr_state is
  63.       when idle =>
  64.         Q <= ('1','1');
  65.         fifo_RdEn <= '0';
  66.         tx <= '1';
  67.         IF fifo_empty='0' AND rst='0' THEN          
  68.           nx_state <= start;
  69.         ELSE          
  70.           nx_state <= idle;
  71.         END IF;
  72.       WHEN start =>
  73.         Q <= ('1','0');
  74.         fifo_RdEn <= '1';
  75.         tx <= '0';
  76.         nx_state <= data;
  77.       WHEN data =>
  78.         Q <= ('0','1');
  79.         fifo_RdEn <= '0';
  80.         tx <= data_val(to_integer(data_count));
  81.         if data_count=to_unsigned(7,3) then
  82.           nx_state <= idle;
  83.         ELSE
  84.           nx_state <= data;
  85.         end if;
  86.  
  87.     end case;
  88.   END process;
  89.  
  90.   fifo_RdClock <= tx_pulse;
  91.   baud_gen: ENTITY work.baud_gen
  92.     PORT MAP(clk,reset=>'0',s_tick=>s_tick);
  93. END working;
  94.  
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