Counter2

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity COUNTER is
    Port (
        clk, reset : in std_logic;
        up_down: inout std_logic;
        q1 : out std_logic_vector ( 3 downto 0)
    );
end COUNTER;

architecture Behavioral of COUNTER is

    begin
        process (clk, reset )
        variable temp1 : integer := 0;
        begin
        if(reset = '1') then
            temp1 := 0;
            up_down <= '1';
        else if(clk' event and clk = '1') then

                    if(up_down = '1') then
                        if (temp1 = 15) then
                            up_down <= '0';
                        else
                            temp1 := temp1 + 1;
                        end if;
                    else
                        if(temp1 = 0) then
                            up_down <= '1';
                        else
                            temp1 := temp1 -1;
                        end if;

                    end if;
        end if;

        q1 <= std_logic_vector(to_unsigned(temp1, q1'length));
        end process;
end architecture Behavioral;