Advertisement
Florii11

registru

Mar 30th, 2021
365
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.all;
  3.  
  4. entity registru is
  5.     port(SLI,SRI,CLK,CLR:in std_logic;
  6.     SEL:in std_logic_vector (1 downto 0);
  7.     D:in std_logic_vector(3 downto 0);
  8.     Q:out std_logic_vector(3 downto 0));
  9. end entity;
  10.  
  11. architecture comportamentala of registru is
  12. begin
  13.     process (CLK,CLR,SEL)
  14.     variable T:std_logic_vector(3 downto 0);
  15.     begin
  16.         if(CLR='0') then
  17.             T:="0000";
  18.         elsif(CLK'event and CLK='1') then
  19.             case SEL is
  20.                 when "00" => T:=T;
  21.                 when "01" => T(0):=T(1);T(1):=T(2);T(2):=T(3);T(3):=SRI;
  22.                 when "10" =>T(3):=T(2);T(2):=T(1);T(1):=T(0);T(0):=SLI;
  23.                 when "11" =>T:=D;
  24.                 when others => T:="0000";
  25.             end case;
  26.         end if;
  27.         Q<=T;
  28.     end process;
  29. end architecture;
Advertisement
RAW Paste Data Copied
Advertisement