registru

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity registru is
    port(SLI,SRI,CLK,CLR:in std_logic;
    SEL:in std_logic_vector (1 downto 0);
    D:in std_logic_vector(3 downto 0);
    Q:out std_logic_vector(3 downto 0));
end entity;

architecture comportamentala of registru is
begin
    process (CLK,CLR,SEL)
    variable T:std_logic_vector(3 downto 0);
    begin
        if(CLR='0') then
            T:="0000";
        elsif(CLK'event and CLK='1') then
            case SEL is
                when "00" => T:=T;
                when "01" => T(0):=T(1);T(1):=T(2);T(2):=T(3);T(3):=SRI;
                when "10" =>T(3):=T(2);T(2):=T(1);T(1):=T(0);T(0):=SLI;
                when "11" =>T:=D;
                when others => T:="0000";
            end case;
        end if;
        Q<=T;
    end process;
end architecture;