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kirill_76rus

d_trg

Mar 15th, 2022
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4. entity d_trig is
  5.     port(
  6.     clk : in std_logic;
  7.     set_i : in std_logic;
  8.     reset_i : in std_logic;
  9.     data_o : out std_logic
  10.     );
  11. end d_trig;
  12.  
  13. architecture behavioral of d_trig is
  14.     signal data_reg : std_logic := '0';
  15. begin
  16.  
  17. d_trg: process(clk, set_i) begin
  18.     if reset_i = '1' then
  19.         if rising_edge(clk) then
  20.             data_o <= '0';
  21.             data_reg <= '0';
  22.         end if;
  23.     elsif set_i = '1' then
  24.         data_o <= '1';
  25.         data_reg <= '1';
  26.     else
  27.         data_o <= data_reg;
  28.     end if;
  29.    
  30. end process d_trg;
  31.  
  32. end architecture behavioral;
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