d_trg

library ieee;
use ieee.std_logic_1164.all;

entity d_trig is
    port(
    clk : in std_logic;
    set_i : in std_logic;
    reset_i : in std_logic;
    data_o : out std_logic
    );
end d_trig;

architecture behavioral of d_trig is
    signal data_reg : std_logic := '0';
begin

d_trg: process(clk, set_i) begin
    if reset_i = '1' then
        if rising_edge(clk) then
            data_o <= '0';
            data_reg <= '0';
        end if;
    elsif set_i = '1' then
        data_o <= '1';
        data_reg <= '1';
    else
        data_o <= data_reg;
    end if;

end process d_trg;

end architecture behavioral;