library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCDto7Segment is
    Port (
        BCD: in STD_LOGIC_VECTOR(3 downto 0);
        SevenSegment: out STD_LOGIC_VECTOR(6 downto 0)
    );
end BCDto7Segment;

architecture Behavioral of BCDto7Segment is


begin
    with BCD select -- A
        SevenSegment(0) <= '0' when "0001"|"0100",
                           '1' when others;
    with BCD select -- B
        SevenSegment(1) <= '0' when "0101"|"0110",
                           '1' when others;
    with BCD select -- C
        SevenSegment(2) <= '0' when "0010",
                           '1' when others;
    with BCD select -- D
        SevenSegment(3) <= '0' when "0001"|"0100"|"0111",
                           '1' when others;
    with BCD select -- E
        SevenSegment(4) <= '1' when "0000"|"0010"|"0110"|"1000",
                           '0' when others;
    with BCD select -- F
        SevenSegment(5) <= '0' when "0001"|"0010"|"0011"|"0111",
                           '1' when others;
    with BCD select -- G
        SevenSegment(6) <= '0' when "0000"|"0001"|"0111",
                           '1' when others;

end Behavioral;