VHDL

////////////////////////////////////////////////////// CONTROL

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY control IS
    PORT (
        clk : IN std_logic;
        IR : IN signed(15 DOWNTO 0);
        reset, C, Z, S, INT : IN std_logic;
        Salu, Sbb, Sbc, Sba : OUT bit_vector(3 DOWNTO 0);
        Sid : OUT bit_vector(2 DOWNTO 0);
        Sa : OUT bit_vector(1 DOWNTO 0);
        LDF, Smar, Smbr, WR, RD, INTA, MIO : OUT BIT
    );
END ENTITY;
ARCHITECTURE rtl OF control IS
    TYPE state_type IS (fetch, dec, wait_1, call_1, call_2, call_3, call_4,
    RET_1, RET_2, RET_3, push, pop_1, pop_2, neg, inc, dec_1, not_1, shr, shl,
    m29, mov_r, mov_rm, add, sub, and_1, or_1, xor_1, in_r, out_io, jump_1, jump_2,
    long_jump, r_st16,  r_adr32, m9,
    mov_arg1_arg2, add_arg1_arg2, sub_arg1_arg2, gethx_arg1_arg2,getlx_arg1_arg2,
    shl_arg1_arg2, shr_arg1_arg2, jmp_etykieta);
    SIGNAL state : state_type;
BEGIN
    PROCESS (clk, reset)
    BEGIN
        IF reset = '1' THEN
            state <= fetch;
        ELSIF (clk'EVENT AND clk = '1') THEN
            CASE state IS
                WHEN fetch =>
                    state <= dec;
                WHEN dec =>
                    CASE IR(15 DOWNTO 13) IS
                        WHEN "000" =>
                            CASE IR(12 DOWNTO 11) IS
                                WHEN "00" =>
                                    IF (INT = '0') THEN
                                        state <= fetch;
                                    ELSE
                                        state <= m9;
                                    END IF;
                                WHEN "01" => state <= wait_1;
                                WHEN "10" => state <= call_1;
                                WHEN "11" => state <= RET_1;
                                WHEN others => state <= fetch;
                        END CASE;
                        WHEN "001" =>
                            CASE IR(12 DOWNTO 8) IS
                                WHEN "00000" => state <= push;
                                WHEN "00001" => state <= pop_1;
                                WHEN "00010" => state <= neg;
                                WHEN "00011" => state <= inc;
                                WHEN "00100" => state <= dec_1;
                                WHEN "00101" => state <= not_1;
                                WHEN "00110" => state <= shr;
                                WHEN "00111" => state <= shl;
                                WHEN "01000" => state <= m29;
                                WHEN "01001" => state <= mov_r;
                                WHEN "01010" => state <= mov_rm;
                                WHEN "01011" => state <= add;
                                WHEN "01100" => state <= sub;
                                WHEN "01101" => state <= and_1;
                                WHEN "01110" => state <= or_1;
                                WHEN "01111" => state <= xor_1;
                                WHEN "10000" => state <= in_r;
                                WHEN "10001" => state <= out_io;
                                WHEN OTHERS => state <= fetch;
                        END CASE;
                        WHEN "010" => state <= jump_1;
                        WHEN "011" => state <= jump_2;

                    WHEN "100" =>
                        case IR(12 downto 8) is
                            when "000000" => state <= mov_arg1_arg2;
                            when "000001" => state <= add_arg1_arg2;
                            when "000010" => state <= sub_arg1_arg2;
                            when "000011" => state <= gethx_arg1_arg2;
                            when "000100" => state <= getlx_arg1_arg2;
                            when "000101" => state <= shl_arg1_arg2;
                            when "000110" => state <= shr_arg1_arg2;
                            when "000111" => state <= jmp_etykieta;
                            WHEN OTHERS => state <= fetch;
                            END CASE;
                        when "101" => state <= r_adr32;
                        when others => state <= fetch;
                        end case;

                WHEN wait_1 =>
                    IF INT = '1' THEN
                        state <= m9;
                    ELSE state <= wait_1;
                    END IF;
                WHEN call_1 => state <= call_2;
                WHEN call_2 => state <= call_3;
                WHEN call_3 => state <= call_4;
                WHEN call_4 =>
                    IF INT = '1' THEN
                        state <= m9;
                    ELSE state <= fetch;
                    END IF;
                when others => state <= fetch;
            END CASE;
        END IF;
    END PROCESS;

    PROCESS (state) BEGIN
    CASE state IS
        WHEN fetch =>
            Sa <= "01"; Sbb <= "0000"; Sba <= "0000"; Sid <= "001"; Sbc <= "0000";
            MIO <= '1'; Smar <= '1'; Smbr <= '0'; WR <= '0'; RD <= '1'; Salu <="0000"; LDF <= '0'; INTA <= '0';
        WHEN dec =>
            Sa <= "00"; Sbb <= "0000"; Sba <= "0000"; Sid <= "000"; Sbc <= "0000";
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '0'; RD <= '0'; Salu <="0000"; LDF <= '0'; INTA <= '0';
        WHEN wait_1 =>
            Sa <= "00"; Sbb <= "0000"; Sba <= "0000"; Sid <= "000"; Sbc <= "0000";
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '0'; RD <= '0'; Salu <="0000"; LDF <= '0'; INTA <= '0';
        WHEN call_1 =>
            Sa <= "10"; Sbb <= "1010"; Sba <= "0000"; Sid <= "011"; Sbc <= "0000";
            MIO <= '1'; Smar <= '1'; Smbr <= '1'; WR <= '1'; RD <= '0'; Salu <="0000"; LDF <= '0'; INTA <= '0';

        WHEN mov_arg1_arg2 =>
            Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
            Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0000"; LDF <= '1'; INTA <= '0';

        WHEN add_arg1_arg2 =>
            Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
            Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0001"; LDF <= '1'; INTA <= '0';

        WHEN sub_arg1_arg2 =>
            Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
            Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0010"; LDF <= '1'; INTA <= '0';



        WHEN gethx_arg1_arg2 =>
            Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
            Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0011"; LDF <= '1'; INTA <= '0';

        WHEN getlx_arg1_arg2 =>
            Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
            Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0100"; LDF <= '1'; INTA <= '0';

        WHEN shl_arg1_arg2 =>
            Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
            Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0101"; LDF <= '1'; INTA <= '0';

        WHEN shr_arg1_arg2 =>
            Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
            Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0110"; LDF <= '1'; INTA <= '0';

        WHEN jmp_etykieta =>
            Sa <= "01"; Sbb <=to_bitvector(std_logic_vector(IR(7 downto 4))); Sba <= "0001"; Sid <= "001";
            Sbc <= to_bitvector(std_logic_vector(IR(3 downto 0)));
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '1'; RD <= '0'; Salu <="0111"; LDF <= '1'; INTA <= '0';





        WHEN OTHERS =>
            Sa <= "00"; Sbb <= "0000"; Sba <= "0000"; Sid <= "000"; Sbc <= "0000";
            MIO <= '1'; Smar <= '0'; Smbr <= '0'; WR <= '0'; RD <= '0'; Salu <="0000"; LDF <= '0'; INTA <= '0';
        END CASE;
    END PROCESS;
END rtl;


////////////////////////////////////////////////////// PROCESOR
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ALU is
port (  A : in signed(7 downto 0);
            B : in signed(7 downto 0);
            Salu : in bit_vector (2 downto 0);
            LDF : in bit;
            clk : in bit;
            Y : out signed (7 downto 0);
            C,Z,S,P : out std_logic
        );
end entity;

architecture rtl of ALU is
   begin
            process (Salu, A, B, clk)
                variable res, AA, BB,CC: signed (16 downto 0);
                variable CF,ZF,SF,PF : std_logic;
                variable i : integer range 0 to 15;
                variable zmienna : integer;

                begin
                AA(8) := A(7);
                AA(7 downto 0) := A;
                BB(8) := B(7);
                BB(7 downto 0) := B;
                CC(0) := CF;
                CC(8 downto 1) := "00000000";

                case Salu is
                    when "000" => res := AA; -- MOV arg1, arg2
                    when "001" => res := AA + BB; -- ADD arg1, arg2
                    when "010" => res := AA - BB; -- SUB arg1, arg2
                    when "011" => res(to_integer(BB) downto 0) := AA(to_integer(BB) downto 0); -- GETHX arg1, arg2

                    when "100" =>
                        zmienna := to_integer(unsigned(BB(3 downto 0)));
                        res(zmienna downto 0) := AA(zmienna downto 0);


                    when "101" => res:= AA sll to_integer(BB); -- SHL arg1, arg2
                    when "110" => res:= AA srl to_integer(BB);-- SHR arg1, arg2
                    --when "1111" => ; -- JMP etykieta


                    when others => res := null;
                end case;
            Y <= res(7 downto 0);
            Z <= ZF;
            S <= SF;
            C <= CF;
            P <= PF;
            if (clk'event and clk='1') then
                    if (LDF='1') then

                            if (res = "00000000") then ZF:='1';
                            else ZF:='0';
                            end if;

                            if (res(7)='1') then SF:='1';
                            else SF:='0';
                            end if;

                            CF := res(8) xor res(7);

                            PF := '0';
                            for i in res'range loop
                                PF:= PF xor res(i);
                            end loop;

                    end if;
            end if;
        end process;
end rtl;


////////////////////////////////////////////////////// REJESTRY
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Rejestry is
port
(
    clk : in std_logic;
    DI : in signed (7 downto 0);
    BA : in signed (7 downto 0);
    Sbb : in signed (3 downto 0);
    Sbc : in signed (3 downto 0);
    Sba : in signed (3 downto 0);
    Sid : in signed (2 downto 0);
    Sa : in signed (1 downto 0);
    BB : out signed (7 downto 0);
    BC : out signed (7 downto 0);
    ADR : out signed (15 downto 0);
    IRout : out signed (7 downto 0)
);
end entity;
architecture rtl of Rejestry is
begin
process (clk, Sbb, Sbc, Sba, Sid, Sa, DI)
        variable IR, TMP, A, B, C, D, E, F: signed (7 downto 0);
        variable AD, PC, SP, ATMP : signed (15 downto 0);
        variable DS, CS : signed (15 downto 0);
begin
        if (clk'event and clk='1') then
            case Sid is
                when "001" => PC := PC + 1;
                when "010" => SP := SP + 1;
                when "011" => AD := AD + 1;
                when "101" => SP := SP - 1;
                when "110" => AD := AD - 1;
                when others =>  null;
            end case;

            case Sba is
                when "0000" => IR := BA;
                when "0001" => TMP := BA;
                when "0010" => A := BA;
                when "0011" => B := BA;
                when "0100" => C := BA;
                when "0101" => D := BA;
                when "0110" => E := BA;
                when "0111" => F := BA;
                when "1000" => AD := BA;
                when "1001" => PC := BA;
                when "1010" => SP := BA;
                when "1011" => ATMP := BA;
                when "1100" => DS := BA;
                when "1101" => CS := BA;

            end case;
        end if;

            case Sbb is
                when "0000" => BB <= DI;
                when "0001" => BB <= TMP;
                when "0010" => BB <= A;
                when "0011" => BB <= B;
                when "0100" => BB <= C;
                when "0101" => BB <= D;
                when "0110" => BB <= E;
                when "0111" => BB <= F;
                when "1000" => BB <= AD;
                when "1001" => BB <= PC;
                when "1010" => BB <= SP;
                when "1011" => BB <= ATMP;
                when "1100" => BB <= DS;
                when "1101" => BB <= CS;

            end case;

            case Sbc is
                when "0000" => BC <= DI;
                when "0001" => BC <= TMP;
                when "0010" => BC <= A;
                when "0011" => BC <= B;
                when "0100" => BC <= C;
                when "0101" => BC <= D;
                when "0110" => BC <= E;
                when "0111" => BC <= F;
                when "1000" => BC <= AD;
                when "1001" => BC <= PC;
                when "1010" => BC <= SP;
                when "1011" => BC <= ATMP;
                when "1100" => BC <= DS;
                when "1101" => BC <= CS;
            end case;

            case Sa is
                when "00" => ADR <= AD;
                when "01" => ADR <= PC;
                when "10" => ADR <= SP;
                when "11" => ADR <= ATMP;
            end case;

IRout <= IR;

end process;
end rtl;


////////////////////////////////////////////////////// ??
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity busint is
port
(
    ADR : in signed(31 downto 0);
    DO : in signed(15 downto 0);
    Smar, Smbr, WRin, RDin : in bit;
    AD : out signed (31 downto 0);
    D : inout signed (15 downto 0);
    DI : out signed(15 downto 0);
    WR, RD : out bit ;
    QWE : in bit;
    SEG : in signed(9 downto 0);
    OFS : in signed(5 downto 0)

);
end entity;

architecture rtl of busint is
    begin
        process(Smar, ADR, Smbr, DO, D, WRin, RDin)
            variable MBRin, MBRout: signed(15 downto 0);
            variable MAR : signed(31 downto 0);
                begin
                    if(Smar='1') then
                        if(QWE = '1') then
                            MAR(15 downto 6) := SEG;
                            MAR(5 downto 0) := OFS;
                        else MAR := ADR;
                        end if;
                    end if;

                    if(Smbr='1') then MBRout := DO; end if;
                    if (RDin='1') then MBRin := D; end if;
                    if (WRin='1') then D <= MBRout;
                    else D <= "ZZZZZZZZZZZZZZZZ";
                end if;
        DI <= MBRin;
        AD <= MAR;
        WR <= WRin;
        RD <= RDin;
end process;
end rtl;