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Ashraf1925

*_bit Comparetor

Jan 7th, 2021
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VHDL 0.65 KB | None | 0 0
  1. --Name : Md Ashraful Islam
  2. --Id   : 180041122
  3. -sec :sec a
  4. LIBRARY ieee;
  5. USE ieee.std_logic_1164.ALL;
  6. ENTITY comparater IS
  7. PORT(a,b  : IN std_logic_vector(7 downto 0);
  8.       agb,aeb,alb :OUT std_logic);
  9.     END comparater;
  10.     ARCHITECCHTURE arc of comaparater IS
  11.     SIGNAL result  : std_logic_vector(2 down to 0);
  12. BEGIN
  13.     Process(a,b)
  14.     BEGIN IF a<b THEN
  15.         result <="001";
  16.         ELSIF a=b THEN
  17.             result <="010";
  18.         ELSIF a>b THEN
  19.             result <="100";
  20.         ELSE
  21.             result <="000";
  22.         END IF;
  23.             agb<=result(2);
  24.         aeb <= result(1);
  25.     alb <=result(0);
  26. END process;
  27. END arc;
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