library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_counter is
port( up,en,clk,clr :in std_logic;
     bcd_out: out std_logic_vector( 3 downto 0));
end bcd_counter;

architecture behaviour of bcd_counter is
signal buffer_bcd : unsigned( 3 downto 0 );
begin
 bcd_out<= std_logic_vector(buffer_bcd);
 clk_in: process(clk,clr)
    begin
        if(clr = '1') then buffer_bcd<="0000";
        else if (en= '1' ) then
                if (rising_edge(clk)) and (up='1') then
                    if (buffer_bcd="1001") then buffer_bcd <="0000";
                    else buffer_bcd<= buffer_bcd+1;
                    end if;
                else if ( rising_edge(clk)) and (up='0') then
                    if (buffer_bcd="0000") then buffer_bcd <="1001";
                    else buffer_bcd <= buffer_bcd-1;
                    end if;
                end if;
                end if;
        end if;
        end if;
    end process clk_in;
end behaviour;