comp_magnitude

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Comp_Magnitude_4bits IS
PORT (
    A : in std_logic_vector (3 DOWNTO 0);
    B : in std_logic_vector (3 DOWNTO 0);
    AGB, AEB, ALB : out bit;
);
END Comp_Magnitude_4bits;

ARCHITECTURE arc OF Comp_Magnitude_4bits is
    SIGNAL S : std_logic_vector (2 DOWNTO 0);
begin
    AGB <= "1" when A > B else "0";
    AEB <= "1" when A = B else "0";
    ALB <= "1" when A < B else "0";
end arc;