Ctrl

entity ctrl is
    Port (  OP : in  STD_LOGIC_VECTOR (4 downto 0);
                ALUOP : out  STD_LOGIC_VECTOR (2 downto 0);
                MemWr : out  STD_LOGIC;
                Mem2Reg : out  STD_LOGIC;
                RegWr : out  STD_LOGIC;
                RegDest : out  STD_LOGIC;
                RegBase : out  STD_LOGIC;
                Branch : out  STD_LOGIC;
                N_En : out  STD_LOGIC;
                OV_En : out  STD_LOGIC;
                Z_En : out  STD_LOGIC;
                C_En : out  STD_LOGIC
                );
end ctrl;

architecture Behavioral of ctrl is

begin
    ALUOP   <=  "000"   when OP = "01000" else
                "001"   when OP = "01010" else
                "010"   when OP = "01100" else
                "011"   when OP = "01110" else
                "100"   when OP = "11011" else
                "101"   when OP = "11101" else
                "110"   when OP = "00011" else
                "111"   when OP = "10100";

    MemWr   <=  '1' when OP = "10001" else '0';

    Mem2Reg <= '1' when OP = "10000" else '0';

    RegWr <= '0' when   (OP = "00110" or
                             OP = "10001") else
                '1';

    Branch <= '1' when OP = "00110" else '0';

    RegBase <= '1';

    RegDest <= '0' when OP = "10000" else '1';

    N_En    <=  '1' when    (OP = "01000" or
                             OP = "01010" or
                             OP = "01100" or
                             OP = "01110") else
                '0';

    OV_En   <= '1' when (OP = "01000" or
                             OP = "01010") else
                '0';

   Z_En <= '1' when (OP = "01000" or
                             OP = "01010" or
                             OP = "01100" or
                             OP = "01110") else
                '0';

   C_En <= '1' when (OP = "01000" or
                             OP = "01010") else
                '0';

end Behavioral;