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compatible tn2313def.inc avra

Oct 22nd, 2013
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  1. ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
  2. ;***** Created: 2005-01-11 10:31 ******* Source: ATtiny2313.xml **********
  3. ;*************************************************************************
  4. ;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
  5. ;*
  6. ;* Number            : AVR000
  7. ;* File Name         : "tn2313def.inc"
  8. ;* Title             : Register/Bit Definitions for the ATtiny2313
  9. ;* Date              : 2005-01-11
  10. ;* Version           : 2.14
  11. ;* Support E-mail    : avr@atmel.com
  12. ;* Target MCU        : ATtiny2313
  13. ;*
  14. ;* DESCRIPTION
  15. ;* When including this file in the assembly program file, all I/O register
  16. ;* names and I/O register bit names appearing in the data book can be used.
  17. ;* In addition, the six registers forming the three data pointers X, Y and
  18. ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
  19. ;* SRAM is also defined
  20. ;*
  21. ;* The Register names are represented by their hexadecimal address.
  22. ;*
  23. ;* The Register Bit names are represented by their bit number (0-7).
  24. ;*
  25. ;* Please observe the difference in using the bit names with instructions
  26. ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
  27. ;* (skip if bit in register set/cleared). The following example illustrates
  28. ;* this:
  29. ;*
  30. ;* in    r16,PORTB             ;read PORTB latch
  31. ;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
  32. ;* out   PORTB,r16             ;output to PORTB
  33. ;*
  34. ;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
  35. ;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
  36. ;* rjmp  TOV0_is_set           ;jump if set
  37. ;* ...                         ;otherwise do something else
  38. ;*************************************************************************
  39.  
  40. ;#ifndef _TN2313DEF_INC_
  41. ;#define _TN2313DEF_INC_
  42.  
  43.  
  44. ;#pragma partinc 0
  45.  
  46. ; ***** SPECIFY DEVICE ***************************************************
  47. .device ATtiny2313
  48. ;#pragma AVRPART ADMIN PART_NAME ATtiny2313
  49. .equ    SIGNATURE_000   = 0x1e
  50. .equ    SIGNATURE_001   = 0x91
  51. .equ    SIGNATURE_002   = 0x0a
  52.  
  53. ;#pragma AVRPART CORE CORE_VERSION V2
  54. ;#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
  55.  
  56.  
  57. ; ***** I/O REGISTER DEFINITIONS *****************************************
  58. ; NOTE:
  59. ; Definitions marked "MEMORY MAPPED"are extended I/O ports
  60. ; and cannot be used with IN/OUT instructions
  61. .equ    SREG    = 0x3f
  62. .equ    SPL = 0x3d
  63. .equ    OCR0B   = 0x3c
  64. .equ    GIMSK   = 0x3b
  65. .equ    EIFR    = 0x3a
  66. .equ    TIMSK   = 0x39
  67. .equ    TIFR    = 0x38
  68. .equ    SPMCSR  = 0x37
  69. .equ    OCR0A   = 0x36
  70. .equ    MCUCR   = 0x35
  71. .equ    MCUSR   = 0x34
  72. .equ    TCCR0B  = 0x33
  73. .equ    TCNT0   = 0x32
  74. .equ    OSCCAL  = 0x31
  75. .equ    TCCR0A  = 0x30
  76. .equ    TCCR1A  = 0x2f
  77. .equ    TCCR1B  = 0x2e
  78. .equ    TCNT1H  = 0x2d
  79. .equ    TCNT1L  = 0x2c
  80. .equ    OCR1AH  = 0x2b
  81. .equ    OCR1AL  = 0x2a
  82. .equ    OCR1BH  = 0x29
  83. .equ    OCR1BL  = 0x28
  84. .equ    CLKPR   = 0x26
  85. .equ    ICR1H   = 0x25
  86. .equ    ICR1L   = 0x24
  87. .equ    GTCCR   = 0x23
  88. .equ    TCCR1C  = 0x22
  89. .equ    WDTCR   = 0x21
  90. .equ    PCMSK   = 0x20
  91. .equ    EEAR    = 0x1e
  92. .equ    EEDR    = 0x1d
  93. .equ    EECR    = 0x1c
  94. .equ    PORTA   = 0x1b
  95. .equ    DDRA    = 0x1a
  96. .equ    PINA    = 0x19
  97. .equ    PORTB   = 0x18
  98. .equ    DDRB    = 0x17
  99. .equ    PINB    = 0x16
  100. .equ    GPIOR2  = 0x15
  101. .equ    GPIOR1  = 0x14
  102. .equ    GPIOR0  = 0x13
  103. .equ    PORTD   = 0x12
  104. .equ    DDRD    = 0x11
  105. .equ    PIND    = 0x10
  106. .equ    USIDR   = 0x0f
  107. .equ    USISR   = 0x0e
  108. .equ    USICR   = 0x0d
  109. .equ    UDR = 0x0c
  110. .equ    UCSRA   = 0x0b
  111. .equ    UCSRB   = 0x0a
  112. .equ    UBRRL   = 0x09
  113. .equ    ACSR    = 0x08
  114. .equ    UCSRC   = 0x03
  115. .equ    UBRRH   = 0x02
  116. .equ    DIDR    = 0x01
  117.  
  118.  
  119. ; ***** BIT DEFINITIONS **************************************************
  120.  
  121. ; ***** PORTB ************************
  122. ; PORTB - Port B Data Register
  123. .equ    PORTB0  = 0 ; Port B Data Register bit 0
  124. .equ    PB0 = 0 ; For compatibility
  125. .equ    PORTB1  = 1 ; Port B Data Register bit 1
  126. .equ    PB1 = 1 ; For compatibility
  127. .equ    PORTB2  = 2 ; Port B Data Register bit 2
  128. .equ    PB2 = 2 ; For compatibility
  129. .equ    PORTB3  = 3 ; Port B Data Register bit 3
  130. .equ    PB3 = 3 ; For compatibility
  131. .equ    PORTB4  = 4 ; Port B Data Register bit 4
  132. .equ    PB4 = 4 ; For compatibility
  133. .equ    PORTB5  = 5 ; Port B Data Register bit 5
  134. .equ    PB5 = 5 ; For compatibility
  135. .equ    PORTB6  = 6 ; Port B Data Register bit 6
  136. .equ    PB6 = 6 ; For compatibility
  137. .equ    PORTB7  = 7 ; Port B Data Register bit 7
  138. .equ    PB7 = 7 ; For compatibility
  139.  
  140. ; DDRB - Port B Data Direction Register
  141. .equ    DDB0    = 0 ; Port B Data Direction Register bit 0
  142. .equ    DDB1    = 1 ; Port B Data Direction Register bit 1
  143. .equ    DDB2    = 2 ; Port B Data Direction Register bit 2
  144. .equ    DDB3    = 3 ; Port B Data Direction Register bit 3
  145. .equ    DDB4    = 4 ; Port B Data Direction Register bit 4
  146. .equ    DDB5    = 5 ; Port B Data Direction Register bit 5
  147. .equ    DDB6    = 6 ; Port B Data Direction Register bit 6
  148. .equ    DDB7    = 7 ; Port B Data Direction Register bit 7
  149.  
  150. ; PINB - Port B Input Pins
  151. .equ    PINB0   = 0 ; Port B Input Pins bit 0
  152. .equ    PINB1   = 1 ; Port B Input Pins bit 1
  153. .equ    PINB2   = 2 ; Port B Input Pins bit 2
  154. .equ    PINB3   = 3 ; Port B Input Pins bit 3
  155. .equ    PINB4   = 4 ; Port B Input Pins bit 4
  156. .equ    PINB5   = 5 ; Port B Input Pins bit 5
  157. .equ    PINB6   = 6 ; Port B Input Pins bit 6
  158. .equ    PINB7   = 7 ; Port B Input Pins bit 7
  159.  
  160.  
  161. ; ***** TIMER_COUNTER_0 **************
  162. ; TIMSK - Timer/Counter Interrupt Mask Register
  163. .equ    OCIE0A  = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable
  164. .equ    TOIE0   = 1 ; Timer/Counter0 Overflow Interrupt Enable
  165. .equ    OCIE0B  = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
  166.  
  167. ; TIFR - Timer/Counter Interrupt Flag register
  168. .equ    OCF0A   = 0 ; Timer/Counter0 Output Compare Flag 0A
  169. .equ    TOV0    = 1 ; Timer/Counter0 Overflow Flag
  170. .equ    OCF0B   = 2 ; Timer/Counter0 Output Compare Flag 0B
  171.  
  172. ; OCR0B - Timer/Counter0 Output Compare Register
  173. .equ    OCR0_0  = 0 ;
  174. .equ    OCR0_1  = 1 ;
  175. .equ    OCR0_2  = 2 ;
  176. .equ    OCR0_3  = 3 ;
  177. .equ    OCR0_4  = 4 ;
  178. .equ    OCR0_5  = 5 ;
  179. .equ    OCR0_6  = 6 ;
  180. .equ    OCR0_7  = 7 ;
  181.  
  182. ; OCR0A - Timer/Counter0 Output Compare Register
  183. ;.equ   OCR0_0  = 0 ;
  184. ;.equ   OCR0_1  = 1 ;
  185. ;.equ   OCR0_2  = 2 ;
  186. ;.equ   OCR0_3  = 3 ;
  187. ;.equ   OCR0_4  = 4 ;
  188. ;.equ   OCR0_5  = 5 ;
  189. ;.equ   OCR0_6  = 6 ;
  190. ;.equ   OCR0_7  = 7 ;
  191.  
  192. ; TCCR0A - Timer/Counter  Control Register A
  193. .equ    WGM00   = 0 ; Waveform Generation Mode
  194. .equ    WGM01   = 1 ; Waveform Generation Mode
  195. .equ    COM0B0  = 4 ; Compare Match Output B Mode
  196. .equ    COM0B1  = 5 ; Compare Match Output B Mode
  197. .equ    COM0A0  = 6 ; Compare Match Output A Mode
  198. .equ    COM0A1  = 7 ; Compare Match Output A Mode
  199.  
  200. ; TCNT0 - Timer/Counter0
  201. .equ    TCNT0_0 = 0 ;
  202. .equ    TCNT0_1 = 1 ;
  203. .equ    TCNT0_2 = 2 ;
  204. .equ    TCNT0_3 = 3 ;
  205. .equ    TCNT0_4 = 4 ;
  206. .equ    TCNT0_5 = 5 ;
  207. .equ    TCNT0_6 = 6 ;
  208. .equ    TCNT0_7 = 7 ;
  209.  
  210. ; TCCR0B - Timer/Counter Control Register B
  211. .equ    TCCR0   = TCCR0B    ; For compatibility
  212. .equ    CS00    = 0 ; Clock Select
  213. .equ    CS01    = 1 ; Clock Select
  214. .equ    CS02    = 2 ; Clock Select
  215. .equ    WGM02   = 3 ;
  216. .equ    FOC0B   = 6 ; Force Output Compare B
  217. .equ    FOC0A   = 7 ; Force Output Compare B
  218.  
  219.  
  220. ; ***** TIMER_COUNTER_1 **************
  221. ; TIMSK - Timer/Counter Interrupt Mask Register
  222. .equ    ICIE1   = 3 ; Timer/Counter1 Input Capture Interrupt Enable
  223. .equ    TICIE   = ICIE1 ; For compatibility
  224. .equ    OCIE1B  = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
  225. .equ    OCIE1A  = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
  226. .equ    TOIE1   = 7 ; Timer/Counter1 Overflow Interrupt Enable
  227.  
  228. ; TIFR - Timer/Counter Interrupt Flag register
  229. .equ    ICF1    = 3 ; Input Capture Flag 1
  230. .equ    OCF1B   = 5 ; Output Compare Flag 1B
  231. .equ    OCF1A   = 6 ; Output Compare Flag 1A
  232. .equ    TOV1    = 7 ; Timer/Counter1 Overflow Flag
  233.  
  234. ; TCCR1A - Timer/Counter1 Control Register A
  235. .equ    WGM10   = 0 ; Pulse Width Modulator Select Bit 0
  236. .equ    PWM10   = WGM10 ; For compatibility
  237. .equ    WGM11   = 1 ; Pulse Width Modulator Select Bit 1
  238. .equ    PWM11   = WGM11 ; For compatibility
  239. .equ    COM1B0  = 4 ; Comparet Ouput Mode 1B, bit 0
  240. .equ    COM1B1  = 5 ; Compare Output Mode 1B, bit 1
  241. .equ    COM1A0  = 6 ; Comparet Ouput Mode 1A, bit 0
  242. .equ    COM1A1  = 7 ; Compare Output Mode 1A, bit 1
  243.  
  244. ; TCCR1B - Timer/Counter1 Control Register B
  245. .equ    CS10    = 0 ; Clock Select bit 0
  246. .equ    CS11    = 1 ; Clock Select 1 bit 1
  247. .equ    CS12    = 2 ; Clock Select1 bit 2
  248. .equ    WGM12   = 3 ; Waveform Generation Mode Bit 2
  249. .equ    CTC1    = WGM12 ; For compatibility
  250. .equ    WGM13   = 4 ; Waveform Generation Mode Bit 3
  251. .equ    ICES1   = 6 ; Input Capture 1 Edge Select
  252. .equ    ICNC1   = 7 ; Input Capture 1 Noise Canceler
  253.  
  254. ; TCCR1C - Timer/Counter1 Control Register C
  255. .equ    FOC1B   = 6 ; Force Output Compare for Channel B
  256. .equ    FOC1A   = 7 ; Force Output Compare for Channel A
  257.  
  258.  
  259. ; ***** WATCHDOG *********************
  260. ; WDTCR - Watchdog Timer Control Register
  261. .equ    WDTCSR  = WDTCR ; For compatibility
  262. .equ    WDP0    = 0 ; Watch Dog Timer Prescaler bit 0
  263. .equ    WDP1    = 1 ; Watch Dog Timer Prescaler bit 1
  264. .equ    WDP2    = 2 ; Watch Dog Timer Prescaler bit 2
  265. .equ    WDE = 3 ; Watch Dog Enable
  266. .equ    WDCE    = 4 ; Watchdog Change Enable
  267. .equ    WDTOE   = WDCE  ; For compatibility
  268. .equ    WDP3    = 5 ; Watchdog Timer Prescaler Bit 3
  269. .equ    WDIE    = 6 ; Watchdog Timeout Interrupt Enable
  270. .equ    WDIF    = 7 ; Watchdog Timeout Interrupt Flag
  271.  
  272.  
  273. ; ***** EXTERNAL_INTERRUPT ***********
  274. ; GIMSK - General Interrupt Mask Register
  275. .equ    PCIE    = 5 ;
  276. .equ    INT0    = 6 ; External Interrupt Request 0 Enable
  277. .equ    INT1    = 7 ; External Interrupt Request 1 Enable
  278.  
  279. ; EIFR - Extended Interrupt Flag Register
  280. .equ    GIFR    = EIFR  ; For compatibility
  281. .equ    PCIF    = 5 ;
  282. .equ    INTF0   = 6 ; External Interrupt Flag 0
  283. .equ    INTF1   = 7 ; External Interrupt Flag 1
  284.  
  285.  
  286. ; ***** USART ************************
  287. ; UDR - USART I/O Data Register
  288. .equ    UDR0    = 0 ; USART I/O Data Register bit 0
  289. .equ    UDR1    = 1 ; USART I/O Data Register bit 1
  290. .equ    UDR2    = 2 ; USART I/O Data Register bit 2
  291. .equ    UDR3    = 3 ; USART I/O Data Register bit 3
  292. .equ    UDR4    = 4 ; USART I/O Data Register bit 4
  293. .equ    UDR5    = 5 ; USART I/O Data Register bit 5
  294. .equ    UDR6    = 6 ; USART I/O Data Register bit 6
  295. .equ    UDR7    = 7 ; USART I/O Data Register bit 7
  296.  
  297. ; UCSRA - USART Control and Status Register A
  298. .equ    USR = UCSRA ; For compatibility
  299. .equ    MPCM    = 0 ; Multi-processor Communication Mode
  300. .equ    U2X = 1 ; Double the USART Transmission Speed
  301. .equ    UPE = 2 ; USART Parity Error
  302. .equ    PE  = UPE   ; For compatibility
  303. .equ    DOR = 3 ; Data overRun
  304. .equ    FE  = 4 ; Framing Error
  305. .equ    UDRE    = 5 ; USART Data Register Empty
  306. .equ    TXC = 6 ; USART Transmitt Complete
  307. .equ    RXC = 7 ; USART Receive Complete
  308.  
  309. ; UCSRB - USART Control and Status Register B
  310. .equ    UCR = UCSRB ; For compatibility
  311. .equ    TXB8    = 0 ; Transmit Data Bit 8
  312. .equ    RXB8    = 1 ; Receive Data Bit 8
  313. .equ    UCSZ2   = 2 ; Character Size
  314. .equ    CHR9    = UCSZ2 ; For compatibility
  315. .equ    TXEN    = 3 ; Transmitter Enable
  316. .equ    RXEN    = 4 ; Receiver Enable
  317. .equ    UDRIE   = 5 ; USART Data register Empty Interrupt Enable
  318. .equ    TXCIE   = 6 ; TX Complete Interrupt Enable
  319. .equ    RXCIE   = 7 ; RX Complete Interrupt Enable
  320.  
  321. ; UCSRC - USART Control and Status Register C
  322. .equ    UCPOL   = 0 ; Clock Polarity
  323. .equ    UCSZ0   = 1 ; Character Size Bit 0
  324. .equ    UCSZ1   = 2 ; Character Size Bit 1
  325. .equ    USBS    = 3 ; Stop Bit Select
  326. .equ    UPM0    = 4 ; Parity Mode Bit 0
  327. .equ    UPM1    = 5 ; Parity Mode Bit 1
  328. .equ    UMSEL   = 6 ; USART Mode Select
  329.  
  330. .equ    UBRR    = UBRRL ; For compatibility
  331.  
  332. ; ***** ANALOG_COMPARATOR ************
  333. ; ACSR - Analog Comparator Control And Status Register
  334. .equ    ACIS0   = 0 ; Analog Comparator Interrupt Mode Select bit 0
  335. .equ    ACIS1   = 1 ; Analog Comparator Interrupt Mode Select bit 1
  336. .equ    ACIC    = 2 ;
  337. .equ    ACIE    = 3 ; Analog Comparator Interrupt Enable
  338. .equ    ACI = 4 ; Analog Comparator Interrupt Flag
  339. .equ    ACO = 5 ; Analog Compare Output
  340. .equ    ACBG    = 6 ; Analog Comparator Bandgap Select
  341. .equ    ACD = 7 ; Analog Comparator Disable
  342.  
  343. ; DIDR - Digital Input Disable Register 1
  344. .equ    AIN0D   = 0 ; AIN0 Digital Input Disable
  345. .equ    AIN1D   = 1 ; AIN1 Digital Input Disable
  346.  
  347.  
  348. ; ***** PORTD ************************
  349. ; PORTD - Data Register, Port D
  350. .equ    PORTD0  = 0 ;
  351. .equ    PD0 = 0 ; For compatibility
  352. .equ    PORTD1  = 1 ;
  353. .equ    PD1 = 1 ; For compatibility
  354. .equ    PORTD2  = 2 ;
  355. .equ    PD2 = 2 ; For compatibility
  356. .equ    PORTD3  = 3 ;
  357. .equ    PD3 = 3 ; For compatibility
  358. .equ    PORTD4  = 4 ;
  359. .equ    PD4 = 4 ; For compatibility
  360. .equ    PORTD5  = 5 ;
  361. .equ    PD5 = 5 ; For compatibility
  362. .equ    PORTD6  = 6 ;
  363. .equ    PD6 = 6 ; For compatibility
  364.  
  365. ; DDRD
  366. .equ    DDD0    = 0 ;
  367. .equ    DDD1    = 1 ;
  368. .equ    DDD2    = 2 ;
  369. .equ    DDD3    = 3 ;
  370. .equ    DDD4    = 4 ;
  371. .equ    DDD5    = 5 ;
  372. .equ    DDD6    = 6 ;
  373.  
  374. ; PIND - Input Pins, Port D
  375. .equ    PIND0   = 0 ;
  376. .equ    PIND1   = 1 ;
  377. .equ    PIND2   = 2 ;
  378. .equ    PIND3   = 3 ;
  379. .equ    PIND4   = 4 ;
  380. .equ    PIND5   = 5 ;
  381. .equ    PIND6   = 6 ;
  382.  
  383.  
  384. ; ***** EEPROM ***********************
  385. ; EEAR - EEPROM Read/Write Access
  386. .equ    EEARL   = EEAR  ; For compatibility
  387. .equ    EEAR0   = 0 ; EEPROM Read/Write Access bit 0
  388. .equ    EEAR1   = 1 ; EEPROM Read/Write Access bit 1
  389. .equ    EEAR2   = 2 ; EEPROM Read/Write Access bit 2
  390. .equ    EEAR3   = 3 ; EEPROM Read/Write Access bit 3
  391. .equ    EEAR4   = 4 ; EEPROM Read/Write Access bit 4
  392. .equ    EEAR5   = 5 ; EEPROM Read/Write Access bit 5
  393. .equ    EEAR6   = 6 ; EEPROM Read/Write Access bit 6
  394.  
  395. ; EEDR - EEPROM Data Register
  396. .equ    EEDR0   = 0 ; EEPROM Data Register bit 0
  397. .equ    EEDR1   = 1 ; EEPROM Data Register bit 1
  398. .equ    EEDR2   = 2 ; EEPROM Data Register bit 2
  399. .equ    EEDR3   = 3 ; EEPROM Data Register bit 3
  400. .equ    EEDR4   = 4 ; EEPROM Data Register bit 4
  401. .equ    EEDR5   = 5 ; EEPROM Data Register bit 5
  402. .equ    EEDR6   = 6 ; EEPROM Data Register bit 6
  403. .equ    EEDR7   = 7 ; EEPROM Data Register bit 7
  404.  
  405. ; EECR - EEPROM Control Register
  406. .equ    EERE    = 0 ; EEPROM Read Enable
  407. .equ    EEPE    = 1 ; EEPROM Write Enable
  408. .equ    EEWE    = EEPE  ; For compatibility
  409. .equ    EEMPE   = 2 ; EEPROM Master Write Enable
  410. .equ    EEMWE   = EEMPE ; For compatibility
  411. .equ    EERIE   = 3 ; EEProm Ready Interrupt Enable
  412. .equ    EEPM0   = 4 ;
  413. .equ    EEPM1   = 5 ;
  414.  
  415.  
  416. ; ***** PORTA ************************
  417. ; PORTA - Port A Data Register
  418. .equ    PORTA0  = 0 ; Port A Data Register bit 0
  419. .equ    PA0 = 0 ; For compatibility
  420. .equ    PORTA1  = 1 ; Port A Data Register bit 1
  421. .equ    PA1 = 1 ; For compatibility
  422. .equ    PORTA2  = 2 ; Port A Data Register bit 2
  423. .equ    PA2 = 2 ; For compatibility
  424.  
  425. ; DDRA - Port A Data Direction Register
  426. .equ    DDA0    = 0 ; Data Direction Register, Port A, bit 0
  427. .equ    DDA1    = 1 ; Data Direction Register, Port A, bit 1
  428. .equ    DDA2    = 2 ; Data Direction Register, Port A, bit 2
  429.  
  430. ; PINA - Port A Input Pins
  431. .equ    PINA0   = 0 ; Input Pins, Port A bit 0
  432. .equ    PINA1   = 1 ; Input Pins, Port A bit 1
  433. .equ    PINA2   = 2 ; Input Pins, Port A bit 2
  434.  
  435.  
  436. ; ***** CPU **************************
  437. ; SREG - Status Register
  438. .equ    SREG_C  = 0 ; Carry Flag
  439. .equ    SREG_Z  = 1 ; Zero Flag
  440. .equ    SREG_N  = 2 ; Negative Flag
  441. .equ    SREG_V  = 3 ; Two's Complement Overflow Flag
  442. .equ    SREG_S  = 4 ; Sign Bit
  443. .equ    SREG_H  = 5 ; Half Carry Flag
  444. .equ    SREG_T  = 6 ; Bit Copy Storage
  445. .equ    SREG_I  = 7 ; Global Interrupt Enable
  446.  
  447. ; SPMCSR - Store Program Memory Control and Status register
  448. .equ    SPMEN   = 0 ; Store Program Memory Enable
  449. .equ    PGERS   = 1 ; Page Erase
  450. .equ    PGWRT   = 2 ; Page Write
  451. .equ    RFLB    = 3 ; Read Fuse and Lock Bits
  452. .equ    CTPB    = 4
  453.  
  454. ; MCUCR - MCU Control Register
  455. .equ    ISC00   = 0 ; Interrupt Sense Control 0 bit 0
  456. .equ    ISC01   = 1 ; Interrupt Sense Control 0 bit 1
  457. .equ    ISC10   = 2 ; Interrupt Sense Control 1 bit 0
  458. .equ    ISC11   = 3 ; Interrupt Sense Control 1 bit 1
  459. .equ    SM0 = 4 ; Sleep Mode Select Bit 0
  460. .equ    SM  = SM0   ; For compatibility
  461. .equ    SE  = 5 ; Sleep Enable
  462. .equ    SM1 = 6 ; Sleep Mode Select Bit 1
  463. .equ    PUD = 7 ; Pull-up Disable
  464.  
  465. ; CLKPR - Clock Prescale Register
  466. .equ    CLKPS0  = 0 ; Clock Prescaler Select Bit 0
  467. .equ    CLKPS1  = 1 ; Clock Prescaler Select Bit 1
  468. .equ    CLKPS2  = 2 ; Clock Prescaler Select Bit 2
  469. .equ    CLKPS3  = 3 ; Clock Prescaler Select Bit 3
  470. .equ    CLKPCE  = 7 ; Clock Prescaler Change Enable
  471.  
  472. ; MCUSR - MCU Status register
  473. .equ    PORF    = 0 ; Power-On Reset Flag
  474. .equ    EXTRF   = 1 ; External Reset Flag
  475. .equ    BORF    = 2 ; Brown-out Reset Flag
  476. .equ    WDRF    = 3 ; Watchdog Reset Flag
  477.  
  478. ; OSCCAL - Oscillator Calibration Register
  479. .equ    CAL0    = 0 ; Oscillatro Calibration Value Bit 0
  480. .equ    CAL1    = 1 ; Oscillatro Calibration Value Bit 1
  481. .equ    CAL2    = 2 ; Oscillatro Calibration Value Bit 2
  482. .equ    CAL3    = 3 ; Oscillatro Calibration Value Bit 3
  483. .equ    CAL4    = 4 ; Oscillatro Calibration Value Bit 4
  484. .equ    CAL5    = 5 ; Oscillatro Calibration Value Bit 5
  485. .equ    CAL6    = 6 ; Oscillatro Calibration Value Bit 6
  486.  
  487. ; GTCCR - General Timer Counter Control Register
  488. .equ    SFIOR   = GTCCR ; For compatibility
  489. .equ    PSR10   = 0 ;
  490.  
  491. ; PCMSK - Pin-Change Mask register
  492. .equ    PCINT0  = 0 ; Pin-Change Interrupt 0
  493. .equ    PCINT1  = 1 ; Pin-Change Interrupt 1
  494. .equ    PCINT2  = 2 ; Pin-Change Interrupt 2
  495. .equ    PCINT3  = 3 ; Pin-Change Interrupt 3
  496. .equ    PCINT4  = 4 ; Pin-Change Interrupt 4
  497. .equ    PCINT5  = 5 ; Pin-Change Interrupt 5
  498. .equ    PCINT6  = 6 ; Pin-Change Interrupt 6
  499. .equ    PCINT7  = 7 ; Pin-Change Interrupt 7
  500.  
  501. ; GPIOR2 - General Purpose I/O Register 2
  502. .equ    GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0
  503. .equ    GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1
  504. .equ    GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2
  505. .equ    GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3
  506. .equ    GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4
  507. .equ    GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5
  508. .equ    GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6
  509. .equ    GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7
  510.  
  511. ; GPIOR1 - General Purpose I/O Register 1
  512. .equ    GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0
  513. .equ    GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1
  514. .equ    GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2
  515. .equ    GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3
  516. .equ    GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4
  517. .equ    GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5
  518. .equ    GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6
  519. .equ    GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7
  520.  
  521. ; GPIOR0 - General Purpose I/O Register 0
  522. .equ    GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0
  523. .equ    GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1
  524. .equ    GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2
  525. .equ    GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3
  526. .equ    GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4
  527. .equ    GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5
  528. .equ    GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6
  529. .equ    GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7
  530.  
  531.  
  532. ; ***** USI **************************
  533. ; USIDR - USI Data Register
  534. .equ    USIDR0  = 0 ; USI Data Register bit 0
  535. .equ    USIDR1  = 1 ; USI Data Register bit 1
  536. .equ    USIDR2  = 2 ; USI Data Register bit 2
  537. .equ    USIDR3  = 3 ; USI Data Register bit 3
  538. .equ    USIDR4  = 4 ; USI Data Register bit 4
  539. .equ    USIDR5  = 5 ; USI Data Register bit 5
  540. .equ    USIDR6  = 6 ; USI Data Register bit 6
  541. .equ    USIDR7  = 7 ; USI Data Register bit 7
  542.  
  543. ; USISR - USI Status Register
  544. .equ    USICNT0 = 0 ; USI Counter Value Bit 0
  545. .equ    USICNT1 = 1 ; USI Counter Value Bit 1
  546. .equ    USICNT2 = 2 ; USI Counter Value Bit 2
  547. .equ    USICNT3 = 3 ; USI Counter Value Bit 3
  548. .equ    USIDC   = 4 ; Data Output Collision
  549. .equ    USIPF   = 5 ; Stop Condition Flag
  550. .equ    USIOIF  = 6 ; Counter Overflow Interrupt Flag
  551. .equ    USISIF  = 7 ; Start Condition Interrupt Flag
  552.  
  553. ; USICR - USI Control Register
  554. .equ    USITC   = 0 ; Toggle Clock Port Pin
  555. .equ    USICLK  = 1 ; Clock Strobe
  556. .equ    USICS0  = 2 ; USI Clock Source Select Bit 0
  557. .equ    USICS1  = 3 ; USI Clock Source Select Bit 1
  558. .equ    USIWM0  = 4 ; USI Wire Mode Bit 0
  559. .equ    USIWM1  = 5 ; USI Wire Mode Bit 1
  560. .equ    USIOIE  = 6 ; Counter Overflow Interrupt Enable
  561. .equ    USISIE  = 7 ; Start Condition Interrupt Enable
  562.  
  563.  
  564.  
  565. ; ***** LOCKSBITS ********************************************************
  566. .equ    LB1 = 0 ; Lockbit
  567. .equ    LB2 = 1 ; Lockbit
  568.  
  569.  
  570. ; ***** FUSES ************************************************************
  571. ; LOW fuse bits
  572. .equ    CKSEL0  = 0 ; Select Clock Source
  573. .equ    CKSEL1  = 1 ; Select Clock Source
  574. .equ    CKSEL2  = 2 ; Select Clock Source
  575. .equ    CKSEL3  = 3 ; Select Clock Source
  576. .equ    SUT0    = 4 ; Select start-up time
  577. .equ    SUT1    = 5 ; Select start-up time
  578. .equ    CKOUT   = 6 ; Clock output
  579. .equ    CKDIV8  = 7 ; Divide clock by 8
  580.  
  581. ; HIGH fuse bits
  582. .equ    BODLEVEL0   = 0 ; Brown-out Detector trigger level
  583. .equ    BODLEVEL1   = 1 ; Brown-out Detector trigger level
  584. .equ    BODLEVEL2   = 2 ; Brown-out Detector trigger level
  585. .equ    EESAVE  = 3 ; EEPROM memory is preserved through chip erase
  586. .equ    WDTON   = 4 ; Watchdog Timer Always On
  587. .equ    SPIEN   = 5 ; Enable Serial programming and Data Downloading
  588. .equ    DWEN    = 6 ; debugWIRE Enable
  589. .equ    RSTDISBL    = 7 ; External reset disable
  590.  
  591. ; EXTENDED fuse bits
  592. .equ    SELFPRGEN   = 0 ; Self Programming Enable
  593.  
  594.  
  595.  
  596. ; ***** CPU REGISTER DEFINITIONS *****************************************
  597. .def    XH  = r27
  598. .def    XL  = r26
  599. .def    YH  = r29
  600. .def    YL  = r28
  601. .def    ZH  = r31
  602. .def    ZL  = r30
  603.  
  604.  
  605.  
  606. ; ***** DATA MEMORY DECLARATIONS *****************************************
  607. .equ    FLASHEND    = 0x03ff    ; Note: Word address
  608. .equ    IOEND   = 0x003f
  609. .equ    SRAM_START  = 0x0060
  610. .equ    SRAM_SIZE   = 128
  611. .equ    RAMEND  = 0x00df
  612. .equ    XRAMEND = 0x0000
  613. .equ    E2END   = 0x007f
  614. .equ    EEPROMEND   = 0x007f
  615. .equ    EEADRBITS   = 7
  616. ;#pragma AVRPART MEMORY PROG_FLASH 2048
  617. ;#pragma AVRPART MEMORY EEPROM 128
  618. ;#pragma AVRPART MEMORY INT_SRAM SIZE 128
  619. ;#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
  620.  
  621.  
  622.  
  623. ; ***** BOOTLOADER DECLARATIONS ******************************************
  624. .equ    NRWW_START_ADDR = 0x0
  625. .equ    NRWW_STOP_ADDR  = 0x3ff
  626. .equ    RWW_START_ADDR  = 0x0
  627. .equ    RWW_STOP_ADDR   = 0x0
  628. .equ    PAGESIZE    = 16
  629.  
  630.  
  631.  
  632. ; ***** INTERRUPT VECTORS ************************************************
  633. .equ    INT0addr    = 0x0001    ; External Interrupt Request 0
  634. .equ    INT1addr    = 0x0002    ; External Interrupt Request 1
  635. .equ    ICP1addr    = 0x0003    ; Timer/Counter1 Capture Event
  636. .equ    OC1Aaddr    = 0x0004    ; Timer/Counter1 Compare Match A
  637. .equ    OC1addr = 0x0004    ; For compatibility
  638. .equ    OVF1addr    = 0x0005    ; Timer/Counter1 Overflow
  639. .equ    OVF0addr    = 0x0006    ; Timer/Counter0 Overflow
  640. .equ    URXCaddr    = 0x0007    ; USART, Rx Complete
  641. .equ    URXC0addr   = 0x0007    ; For compatibility
  642. .equ    UDREaddr    = 0x0008    ; USART Data Register Empty
  643. .equ    UDRE0addr   = 0x0008    ; For compatibility
  644. .equ    UTXCaddr    = 0x0009    ; USART, Tx Complete
  645. .equ    UTXC0addr   = 0x0009    ; For compatibility
  646. .equ    ACIaddr = 0x000a    ; Analog Comparator
  647. .equ    PCIaddr = 0x000b    ;
  648. .equ    OC1Baddr    = 0x000c    ;
  649. .equ    OC0Aaddr    = 0x000d    ;
  650. .equ    OC0Baddr    = 0x000e    ;
  651. .equ    USI_STARTaddr   = 0x000f    ; USI Start Condition
  652. .equ    USI_OVFaddr = 0x0010    ; USI Overflow
  653. .equ    ERDYaddr    = 0x0011    ;
  654. .equ    WDTaddr = 0x0012    ; Watchdog Timer Overflow
  655.  
  656. .equ    INT_VECTORS_SIZE    = 19    ; size in words
  657.  
  658. ;#endif  /* _TN2313DEF_INC_ */
  659.  
  660. ; ***** END OF FILE ******************************************************
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