LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.tse_ddio_out;

ENTITY top IS
  PORT
    (
      clk   : IN std_logic;
      res_n : IN std_logic;

      ...

      enet0_gtx_clk : OUT std_logic;
      enet0_mdc     : OUT std_logic;
      enet0_mdio    : INOUT  std_logic;
      enet0_res_n   : OUT std_logic;
      enet0_rx_clk  : IN std_logic;
      enet0_rx_data : IN std_logic_vector(3 DOWNTO 0);
      enet0_rx_dv   : IN std_logic;
      enet0_tx_data : OUT std_logic_vector(3 DOWNTO 0);
      enet0_tx_en   : OUT std_logic;

      ...
    );
end ENTITY;

architecture arch OF top IS

  COMPONENT camera IS
    PORT (
      ...

      clk_clk : IN std_logic := 'X'; -- clk
      reset_reset_n : IN    std_logic := 'X'; -- reset_n

      tse_mac_mdio_connection_mdc         : OUT   std_logic;                                        -- mdc
      tse_mac_mdio_connection_mdio_in     : IN    std_logic                     := 'X';             -- mdio_in
      tse_mac_mdio_connection_mdio_out    : OUT   std_logic;                                        -- mdio_out
      tse_mac_mdio_connection_mdio_oen    : OUT   std_logic;                                        -- mdio_oen
      tse_mac_rgmii_connection_rgmii_in   : IN    std_logic_vector(3 DOWNTO 0)  := (OTHERS => 'X'); -- rgmii_in
      tse_mac_rgmii_connection_rgmii_out  : OUT   std_logic_vector(3 DOWNTO 0);                     -- rgmii_out
      tse_mac_rgmii_connection_rx_control : IN    std_logic                     := 'X';             -- rx_control
      tse_mac_rgmii_connection_tx_control : OUT   std_logic;                                        -- tx_control
      tse_mac_status_connection_set_10    : IN    std_logic                     := 'X';             -- set_10
      tse_mac_status_connection_set_1000  : IN    std_logic                     := 'X';             -- set_1000
      tse_mac_status_connection_eth_mode  : OUT   std_logic;                                        -- eth_mode
      tse_mac_status_connection_ena_10    : OUT   std_logic;                                        -- ena_10
      tse_pcs_mac_rx_clock_connection_clk : IN    std_logic                     := 'X';             -- clk
      tse_pcs_mac_tx_clock_connection_clk : IN    std_logic                     := 'X';             -- clk

      ...

      tse_pll_125_clk               : OUT std_logic;        -- clk
      tse_pll_25_clk                : OUT std_logic;        -- clk
      tse_pll_2p5_clk               : OUT std_logic;        -- clk
      tse_pll_areset_conduit_export : IN  std_logic := 'X'; -- export

      ...
    );
  end COMPONENT;

  ...

  SIGNAL mdc, mdio_in, mdio_oen, mdio_out : std_logic;
  SIGNAL tse_125_clk, tse_25_clk, tse_2p5_clk, locked : std_logic;
  SIGNAL eth_mode, ena_10 : std_logic;
  SIGNAL tx_clk : std_logic;

BEGIN

  mdio_in     <= enet0_mdio;
  enet0_mdc   <= mdc;
  enet0_mdio  <= 'Z' WHEN mdio_oen = '1' ELSE mdio_out;
  enet0_res_n <= res_n;

  tx_clk <= tse_125_clk WHEN eth_mode = '1' ELSE -- Gb mode
        tse_2p5_clk WHEN eth_mode = '0' and ena_10 = '1' ELSE -- 10Mb mode
            tse_25_clk; -- 100Mb mode

  ddio_out : ENTITY tse_ddio_out
    PORT MAP(
      datain_h   => "1",
      datain_l   => "0",
      outclock   => tx_clk,
      dataout(0) => enet0_gtx_clk
    );

  u0 : COMPONENT camera
    PORT MAP (
      clk_clk                             => clk,
      reset_reset_n                       => res_n,

      ...

      tse_mac_mdio_connection_mdc         => mdc,
      tse_mac_mdio_connection_mdio_in     => mdio_in,
      tse_mac_mdio_connection_mdio_out    => mdio_out,
      tse_mac_mdio_connection_mdio_oen    => mdio_oen,
      tse_mac_rgmii_connection_rgmii_in   => enet0_rx_data,
      tse_mac_rgmii_connection_rgmii_out  => enet0_tx_data,
      tse_mac_rgmii_connection_rx_control => enet0_rx_dv,
      tse_mac_rgmii_connection_tx_control => enet0_tx_en,
      tse_mac_status_connection_set_10    => 'X',
      tse_mac_status_connection_set_1000  => 'X',
      tse_mac_status_connection_eth_mode  => eth_mode,
      tse_mac_status_connection_ena_10    => ena_10,
      tse_pcs_mac_rx_clock_connection_clk => enet0_rx_clk,
      tse_pcs_mac_tx_clock_connection_clk => tx_clk,

      ...
  );

...

END ARCHITECTURE;