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portaAND

Jul 30th, 2020
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  1. --PORTA AND 3 ENTRADAS
  2. --ENTRADAS: E1, E2, E3 (in bit)
  3. --SAIDAS:   S1 (out bit)
  4. --AUTORES: MARCOS MEIRA, JOÃO VITOR, SALLATIEL FERNANDES
  5. --DATA: 04/03/2020
  6.  
  7. entity portaAND is
  8.     port (E1, E2, E3: in bit;
  9.           S1: out bit);
  10. end portaAND;
  11.  
  12. architecture arquitetura of portaAND is
  13. begin
  14.     S1 <= E1 and E2 and E3;
  15. end arquitetura;
  16.  
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