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Lab3_pkg

Apr 11th, 2022
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VHDL 2.45 KB | None | 0 0
  1.  
  2. LIBRARY IEEE;
  3. USE IEEE.STD_LOGIC_1164.ALL;
  4. USE IEEE.NUMERIC_STD.ALL;
  5. PACKAGE ITCE364Project_lab3 IS
  6.  
  7.   ----------------------Constant------------------------------------
  8.   CONSTANT length : integer := 8;
  9.   CONSTANT g_length : integer := 5;
  10.   CONSTANT opcode : integer := 8;
  11.   CONSTANT address : integer := 3;
  12.   CONSTANT clk_period : time := 200 ns;
  13.   CONSTANT clk_period_half : time := 100 ns;
  14.  
  15.   ----------------------Type----------------------------------------
  16.   TYPE rom_type IS ARRAY(0 TO 7) OF std_logic_vector(length - 1 DOWNTO 0);
  17.   TYPE reg_array IS ARRAY(address DOWNTO 0) OF std_logic_vector(length - 1 DOWNTO 0);
  18.   ----------------------Data in rom ------------------------------------
  19.   CONSTANT rom : rom_type := (
  20.     0 => "00000001",
  21.     1 => "00000010",
  22.     2 => "00000100",
  23.     3 => "00001000",
  24.     4 => "00010000",
  25.     5 => "00100000",
  26.     6 => "01000000",
  27.     7 => "10000000");
  28.  
  29.     CONSTANT inbusrom : rom_type := (
  30.       0 => "00001000",
  31.       1 => "00000010",
  32.       2 => "11110000",
  33.       3 => "11100000",
  34.       4 => "11110000",
  35.       5 => "00001000",
  36.       6 => "10101010",
  37.       7 => "10000000");
  38.   ----------------------Data in register ------------------------------------
  39.  
  40.  
  41. END PACKAGE;
  42. LIBRARY IEEE;
  43. USE IEEE.STD_LOGIC_1164.ALL;
  44. USE IEEE.NUMERIC_STD.ALL;
  45. PACKAGE ITCE364Project_lab3 IS
  46.  
  47.   ----------------------Constant------------------------------------
  48.   CONSTANT length : integer := 8;
  49.   CONSTANT g_length : integer := 5;
  50.   CONSTANT opcode : integer := 8;
  51.   CONSTANT address : integer := 3;
  52.   CONSTANT clk_period : time := 200 ns;
  53.   CONSTANT clk_period_half : time := 100 ns;
  54.  
  55.   ----------------------Type----------------------------------------
  56.   TYPE rom_type IS ARRAY(0 TO 7) OF std_logic_vector(length - 1 DOWNTO 0);
  57.   TYPE reg_array IS ARRAY(address DOWNTO 0) OF std_logic_vector(length - 1 DOWNTO 0);
  58.   ----------------------Data in rom ------------------------------------
  59.   CONSTANT rom : rom_type := (
  60.     0 => "00000001",
  61.     1 => "00000010",
  62.     2 => "00000100",
  63.     3 => "00001000",
  64.     4 => "00010000",
  65.     5 => "00100000",
  66.     6 => "01000000",
  67.     7 => "10000000");
  68.  
  69.     CONSTANT inbusrom : rom_type := (
  70.       0 => "00001000",
  71.       1 => "00000010",
  72.       2 => "11110000",
  73.       3 => "11100000",
  74.       4 => "11110000",
  75.       5 => "00001000",
  76.       6 => "10101010",
  77.       7 => "10000000");
  78.   ----------------------Data in register ------------------------------------
  79.  
  80.  
  81. END PACKAGE;
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