-- Johannes Jansson
-- 900921-2839
-- johjans@student.chalmers.se
-- Hand-in 2.5

LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cnt74163 IS
  PORT (clock, clear, load, enablep, enablet: IN  STD_LOGIC;
        d:                                    IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
        q:                                    OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        rco:                                  OUT STD_LOGIC);
END cnt74163;

ARCHITECTURE arch_cnt74163 OF cnt74163 IS
  signal qnext,qcopy: std_logic_vector(3 downto 0);
BEGIN
  PROCESS(clock) BEGIN
    if clock'event and clock = '1' then
      qcopy <= qnext;
    end if;
  end process;
  q <= qcopy;
  process(qcopy,d,clear,load,enablep,enablet) begin
    rco <= '0';
    if qcopy = "1111" and enablet = '1' then
      rco <= '1';
    end if;
    if clear = '0' then
      qnext <= (others => '0');
    elsif load = '0' then
      qnext <= d;
    elsif enablep = '1' and enablet = '1' then
      qnext <= qcopy + '1';
    else
      qnext <= qcopy;
    end if;
  end process;
end arch_cnt74163;