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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 27.08.2021 22:09:42
- -- Design Name:
- -- Module Name: MUX - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool Versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx leaf cells in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity MUX is
- -- Port ( );
- Port(
- A: in std_logic_vector (3 downto 0);
- B: in std_logic_vector (3 downto 0);
- C: in std_logic_vector (3 downto 0);
- D: in std_logic_vector (3 downto 0);
- S: out std_logic_vector (3 downto 0);
- Sel: in std_logic_vector (1 downto 0)
- );
- end MUX;
- architecture Behavioral of MUX is
- begin
- process(A,B,C,D,Sel)
- begin
- if Sel = "00"
- then
- S <= A;
- elsif Sel = "01"
- then
- S <= B;
- elsif Sel = "10"
- then
- S <= C;
- else
- S <= D;
- end if;
- end process;
- end Behavioral;
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