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Aethox

muxrefresco

Sep 7th, 2021
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VHDL 1.39 KB | None | 0 0
  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 27.08.2021 22:09:42
  6. -- Design Name:
  7. -- Module Name: MUX - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20.  
  21.  
  22. library IEEE;
  23. use IEEE.STD_LOGIC_1164.ALL;
  24.  
  25. -- Uncomment the following library declaration if using
  26. -- arithmetic functions with Signed or Unsigned values
  27. --use IEEE.NUMERIC_STD.ALL;
  28.  
  29. -- Uncomment the following library declaration if instantiating
  30. -- any Xilinx leaf cells in this code.
  31. --library UNISIM;
  32. --use UNISIM.VComponents.all;
  33.  
  34. entity MUX is
  35. --  Port ( );
  36. Port(
  37.     A: in std_logic_vector (3 downto 0);
  38.     B: in std_logic_vector (3 downto 0);
  39.     C: in std_logic_vector (3 downto 0);
  40.     D: in std_logic_vector (3 downto 0);
  41.     S: out std_logic_vector (3 downto 0);
  42.     Sel: in std_logic_vector (1 downto 0)  
  43. );
  44. end MUX;
  45.  
  46. architecture Behavioral of MUX is
  47.  
  48. begin
  49. process(A,B,C,D,Sel)
  50.  
  51. begin
  52.  
  53. if Sel = "00"
  54.     then
  55.     S <= A;
  56. elsif Sel = "01"
  57.     then
  58.     S <= B;
  59. elsif Sel = "10"
  60.     then
  61.     S <= C;
  62. else
  63.     S <= D;
  64.     end if;
  65.    
  66. end process;
  67.  
  68.  
  69. end Behavioral;
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