VHDL1CODE

Entity FADDER is
port(A,B,Cin: in STD_LOGIC;
    Cout,S: out STD_LOGIC);
End FADDER;

Architecture FA of FADDER is
Signal P,G;
begin
P<=A xor B;
G<=A and B;
S<=P xor Cin;
Cout<=G or (P and Cin);
end FA;

Entity RC5 is
port(A,B: in STD_LOGIC_VECTOR(4 downto 0);
    Cin: in STD_LOGIC;
    S: out STD_LOGIC_VECTOR(5 downto 0));
end RC5;

Architecture Behavioral of RC5 is
Component FADDER is
port(A,B,Cin: in STD_LOGIC;
    Cout,S: out STD_LOGIC);
End Component;
Signal C:STD_LOGIC_VECTOR(3 downto 0);
begin
FA0: FADDER port map(A(0),B(0),'0',C(0),S(0));
FA0: FADDER port map(A(1),B(1),C(0),C(1),S(2));
FA0: FADDER port map(A(2),B(2),C(1),C(2),S(2));
FA0: FADDER port map(A(3),B(3),C(2),C(3),S(3));
FA0: FADDER port map(A(4),B(4),C(3),S(4),S(3));
end Behavioral;

Entity compl is
port(A,B: in STD_LOGIC_VECTOR(3 downto 0);
    CompA,CompaB: out STD_LOGIC_VECTOR(4 downto 0));
end compl;

Architecture Behavioral of compl is
Component RC5 is
port(A,B: in STD_LOGIC_VECTOR(3 downto 0);
    Cin: in STD_LOGIC;
    S: out STD_LOGIC_VECTOR(5 downto 0));
End Component
Signal XA, XB: STD_LOGIC_VECTOR(4 downto 0);
Begin
XA<=A(3)&A;
XB<=B(3)&B;
Rc5_1: RC5 port map(not(XA),"00001",'0',CompA);
Rc5_2: RC5 port map(not(XB),"00001",'0',CompB);
end Behavioral