LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY control_unit IS
    PORT(add_V_H, MSB_sum,
         CNTn_is0_H, CNTn_is1_H, CNTn_is2_H, CNTA_is1023_H,
         CNTn_sign_H,
         Clock, START, Resetn : IN STD_LOGIC;

         memA_WR_H, memA_RD_H, memA_CS_H,
         memB_WR_H, memB_RD_H, memB_CS_H,
         mux2to1_sign_H, mux2to1_MINMAX, mux2to1_V_H, mux2to1_DONE_H,
         regFilter_RST_H, regAvg_RST_H,
         CNT_RST_H,
         regAvg_EN_H,
         CNTn_EN_H, CNTn1_EN_H, CNTn3_EN_H, CNTA_EN_H,
         addFilter_sub_H,
         DONE_out : OUT STD_LOGIC;

         mux4to1_sel, mux4to1_CNT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END control_unit;

ARCHITECTURE behavior OF control_unit IS

    TYPE STATE_TYPE IS (IDLE, LOAD_A, LOAD_Xn1, LOAD_Xn_EN_AVG, LOAD_Xn3, SIGN, WAIT_SIGN, OVERFLOW_MIN, OVERFLOW_MAX, WRITE_B, COUNT, DONE);
    SIGNAL state : STATE_TYPE;

BEGIN
    state_updating: PROCESS(Resetn,Clock)
    BEGIN
        IF Resetn='0' THEN
            state <= IDLE;
        ELSIF (Clock'EVENT AND Clock='1') THEN
            CASE state IS

                WHEN IDLE =>
                    IF START='1' THEN
                        state <= LOAD_A;
                    ELSE
                        state <= IDLE;
                    END IF;

                WHEN LOAD_A =>
                    IF CNTA_is1023_H='1' THEN
                        state <= LOAD_Xn1;
                    ELSE
                        state <= LOAD_A;
                    END IF;

                WHEN LOAD_Xn1 =>
                    state <= LOAD_Xn_EN_AVG;

                WHEN LOAD_Xn_EN_AVG =>
                    IF (CNTn_is0_H OR CNTn_is1_H OR CNTn_is2_H)='1' THEN
                        IF CNTn_sign_H='1' THEN
                          state <= SIGN;
                      ELSE
                        state <= WAIT_SIGN;
                      END IF;
                    ELSE
                        state <= LOAD_Xn3;
                    END IF;

                WHEN LOAD_Xn3 =>
                    IF CNTn_sign_H='1' THEN
                        state <= SIGN;
                    ELSE
                      state <= WAIT_SIGN;
                    END IF;

                WHEN SIGN =>
                    state <= WAIT_SIGN;

                WHEN WAIT_SIGN =>
                  IF add_V_H='1' THEN
                        IF MSB_sum='0' THEN
                            state <= OVERFLOW_MAX;
                        ELSE
                            state <= OVERFLOW_MIN;
                        END IF;
                    ELSE
                        state <= WRITE_B;
                    END IF;

                WHEN OVERFLOW_MAX =>
                    IF CNTn_is0_H='1' THEN
                        state <= DONE;
                    ELSE
                        state <= COUNT;
                    END IF;

                WHEN OVERFLOW_MIN =>
                    IF CNTn_is0_H='1' THEN
                        state <= DONE;
                    ELSE
                        state <= COUNT;
                    END IF;

                WHEN WRITE_B =>
                    IF CNTn_is0_H='1' THEN
                        state <= DONE;
                    ELSE
                        state <= COUNT;
                    END IF;

                WHEN COUNT =>
                    IF CNTn_is1_H='1' THEN
                        state <= LOAD_Xn_EN_AVG;
                    ELSE
                        state <= LOAD_Xn1;
                    END IF;

                WHEN DONE =>
                    IF START='1' THEN
                        state <= DONE;
                    ELSE
                        state <= IDLE;
                    END IF;

                WHEN OTHERS =>
                    state <= IDLE;
            END CASE;
        END IF;
    END PROCESS state_updating;

    output_generation: PROCESS(state)
    BEGIN
        memA_WR_H <= '0'; memA_RD_H <= '0'; memA_CS_H <= '0';
        memB_WR_H <= '0'; memB_RD_H <= '0'; memB_CS_H <= '0';
        mux2to1_sign_H <= '0'; mux2to1_MINMAX <= '0'; mux2to1_V_H <= '0'; mux2to1_DONE_H <= '0';
        regFilter_RST_H <= '0'; regAvg_RST_H <= '0';
        CNT_RST_H <= '0';
        regAvg_EN_H <= '0';
        CNTn_EN_H <= '0'; CNTn1_EN_H <= '0'; CNTn3_EN_H <= '0'; CNTA_EN_H <= '0';
        addFilter_sub_H <= '0';
        DONE_out <= '0';

        mux4to1_sel <= "00"; mux4to1_CNT <= "00";

        CASE state IS

            WHEN IDLE =>
                regFilter_RST_H <= '1';
                regAvg_RST_H <= '1';
                CNT_RST_H <= '1';


            WHEN LOAD_A =>
                memA_CS_H <= '1';
                memA_WR_H <= '1';
                CNTA_EN_H <= '1';
                regFilter_RST_H <= '1';

            WHEN LOAD_Xn1 =>
                memA_RD_H <= '1';
                mux4to1_CNT <= "01";
                memA_CS_H <= '1';

            WHEN LOAD_Xn_EN_AVG =>
               mux4to1_sel <= "01";
               regAvg_EN_H <= '1';
               mux4to1_CNT <= "10";
               memA_CS_H <= '1';
                   memA_RD_H <= '1';

            WHEN LOAD_Xn3 =>
                mux4to1_sel <= "10";
                addFilter_sub_H <= '1';
                mux4to1_CNT <= "11";
                memA_CS_H <= '1';
                memA_RD_H <= '1';

            WHEN SIGN =>
                mux4to1_sel <= "11";
                mux2to1_sign_H <='1';
                addFilter_sub_H <= '1';

            WHEN WAIT_SIGN =>
                mux4to1_sel <= "11";
                  mux2to1_sign_H <='1';
                  addFilter_sub_H <= '0';

            WHEN OVERFLOW_MIN =>
                mux2to1_MINMAX <= '1';
                mux2to1_V_H <= '1';
                memB_CS_H <= '1';
                memB_WR_H <= '1';
                mux4to1_CNT <= "10";

            WHEN OVERFLOW_MAX =>
                mux2to1_MINMAX <= '0';
                mux2to1_V_H <= '1';
                memB_CS_H <= '1';
                memB_WR_H <= '1';
                mux4to1_CNT <= "10";

            WHEN WRITE_B =>
                memB_CS_H <= '1';
                memB_WR_H <= '1';
                mux4to1_CNT <= "10";

            WHEN COUNT =>
              regFilter_RST_H <= '1';
                CNTn_EN_H <= '1';
                CNTn1_EN_H <= '1';
                CNTn3_EN_H <= '1';

            WHEN DONE =>
                DONE_out <= '1';
                mux2to1_DONE_H <= '1';

        END CASE;
    END PROCESS output_generation;
END behavior;