#include <__cross_studio_io.h>
#include "stm32f4xx.h"
#include "system_stm32f4xx.h"
#include <math.h>

void TIM2_IRQHandler(void)
{
  debug_printf("test!\n");
}

int BIT(int input)
{
  return pow(2, input);;
}

void main(void)
{
  RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;    // enable TIM2 clock
  RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;   // enable GPIOA

  TIM2->CCER = 0;
  TIM2->CR1 = 0;
  TIM2->CCMR1 = 0;
  TIM2->CCMR2 = 0;

  // CH1 is connected to TI1 input
  TIM2->CR2 = BIT(7) ;

  // set CCMR1 CC1S to 01 (set active input TI1)
  /// 01: CC1 channel is configured as input, IC1 is mapped on TI1.
  TIM2->CCMR1 &= ~BIT(1);
  TIM2->CCMR1 |= BIT(0);

  // set CCMR1 CC2S to 10 (set active input TI1)
  /// 10: CC2 channel is configured as input, IC2 is mapped on TI1
  TIM2->CCMR1 |= BIT(9);
  TIM2->CCMR1 &= ~BIT(8);

  // select the active polarity on TI1FP1. write CC1P to 0 (active on rising edge)
  ///0: non-inverted: capture is done on a rising edge of IC1.
  TIM2->CCER &= ~BIT(5);

  // select the active polarity on TI1FP2. write CC2P to 1 (active on falling edge)
  ///1: inverted: capture is done on a falling edge of IC1
  TIM2->CCER |= BIT(1) ;

  //select valid trigger input: write TS to 101 in SMCR (Slave Mode Config Register). meaning we should reset when TI1 triggers
  /// 101: Filtered Timer Input 1 (TI1FP1)
  TIM2->SMCR |= BIT(6) | BIT(4) ;
  TIM2->SMCR &= ~BIT(5);

  // write SMS to 100 in SMCR: slave controller in reset mode
  ///100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers
  TIM2->SMCR &= ~BIT(0);
  TIM2->SMCR &= ~BIT(1) ;
  TIM2->SMCR |= BIT(2);

  //enable CC modules
  NVIC->ISER[0] |= 1 << TIM2_IRQn;
  TIM2->CCER |= (BIT(0) | BIT(4));
  TIM2->CR1 |= 1; // enable TIM2
  TIM2->DIER= BIT(2) | BIT(1) | BIT(0);
  TIM2->EGR = BIT(2);

  debug_printf("hello world\n");

  while (1)
  {
  debug_printf("R: %d\n", TIM2->CCR1);
  }

  debug_exit(0);
}