tb_top_level.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity tb_top_level is

end entity tb_top_level;

architecture behavioral of tb_top_level is

    component top_level is
        port (
            clk  : in std_logic;
            srst : in std_logic;

            port_a : in std_logic_vector(7 downto 0));
    end component top_level;

    -- inputs
    signal clk    : std_logic                    := '0';
    signal srst   : std_logic                    := '0';
    signal port_a : std_logic_vector(7 downto 0) := (others => '0');

    -- clock period
    constant clk_period : time := 10 ns;

begin  -- architecture behavioral

    -- unit under test
    uut : top_level
        port map (
            clk  => clk,
            srst => srst,

            port_a => port_a);

    -- clock
    clk_process : process is
    begin
        clk <= '0';
        wait for clk_period / 2;
        clk <= '1';
        wait for clk_period / 2;
    end process clk_process;

    -- stimulus
    stim_process : process is
    begin
        -- hold reset state for 100 ns
       srst <= '1';
       wait for 100 ns;
       srst <= '0';
         port_a <= "10101010";
       wait;
   end process stim_process;
end architecture behavioral;