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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_arith.all;
- use ieee.std_logic_unsigned.all;
- entity address_decoder is
- Port (
- a11 : In std_logic;
- a10 : In std_logic;
- a9 : In std_logic;
- a8 : In std_logic;
- rd : In std_logic;
- wr : In std_logic;
- cs_ram : Out std_logic;
- cs_adc : Out std_logic;
- lcd_en : Out std_logic;
- lcd_rw : Out std_logic;
- lcd_rs : Out std_logic
- );
- attribute LOC : string;
- attribute LOC of cs_adc : signal is "P19";
- attribute LOC of lcd_en : signal is "P18";
- attribute LOC of lcd_rw : signal is "P17";
- attribute LOC of lcd_rs : signal is "P16";
- attribute LOC of cs_ram : signal is "P15";
- attribute LOC of rd : signal is "P5";
- attribute LOC of wr : signal is "P6";
- attribute LOC of a11 : signal is "P7";
- attribute LOC of a10 : signal is "P8";
- attribute LOC of a9 : signal is "P9";
- attribute LOC of a8 : signal is "P4";
- end address_decoder;
- architecture behave of address_decoder is begin
- -- implement the functionality here
- -- hvis a11 (el a8?) = 1, skal cs_ram gå lav
- --cs_ram <= a11;
- cs_ram <= NOT (a11);
- --hvis a11 = 0 og a10 = 1, skal cs_adc gå lav
- cs_adc <= NOT( NOT(a11) AND a10 );
- --LCD a11-a10-a9-a8
- lcd_rw <= a8 AND ( NOT(a11) AND NOT(a10) );
- lcd_rs <= a9 AND ( NOT(a11) AND NOT(a10) );
- --not((not a11 and not a10) and not(wr and rd))
- --lcd_en <= NOT((NOT a11 AND NOT a10) AND NOT(wr AND rd));
- lcd_en <= (a11 NOR a10) AND (wr XOR rd);
- --lcd_en <= ((wr NAND rd) NAND ( (NOT(a11)) AND (NOT(a10)) ) ) NAND ((wr NAND rd) NAND ( (NOT(a11)) AND (NOT(a10)) ));
- --lcd_en <= (wr NAND rd) AND ( (NOT(a11)) AND (NOT(a10)) );
- end behave;
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