architecture SYNTHESIS of DESIGN is
    type STATE_TYPE is (..);
    signal STATE: STATE_TYPE;

    signal COUNTER: UNSIGNED(..);
    signal ROW, COLUMN: UNSIGNED(..);
begin

    process (CLOCK) is
    begin
        if rising_edge(CLOCK) then
            case STATE is
                when Z1 =>
                    STATE <= Z2;
                    COUNTER <= 100;


                when Z2 =>
                    if to_integer(COUNTER) = 0 then
                        ROW <= to..(0);
                        COLUMN <= to..(0);
                        STATE <= Z3;
                    else
                        COUNTER <= COUNTER -1;
                    end if;


                when Z3 =>
                    if to_integer(COLUMN) = ..max.. then
                        if to_integer(ROW) = ..max.. then
                            STATE <= Z1;
                        else
                            -- Next row
                            ROW <= ROW + 1;
                        end if;
                    else
                        -- Scan pixel
                        COLUMN <= COLUMN + 1;
                    end if;
            end case;
        end if;
    end process;

end architecture SYNTHESIS;