Contador

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity Contador is
    Port ( UP_DW : in  STD_LOGIC;
           CLK_In : in  STD_LOGIC;
           Q : out std_logic_vector (3 downto 0)
             );
end Contador;

architecture Behavioral of Contador is

signal j,k, Qaux : std_logic_vector (3 downto 0);
signal y : std_logic;


    COMPONENT FF_JK --DECLARACIÓN DEL COMPONENTE FLIP-FLOP J-K
    PORT(
        J : IN std_logic;
        K : IN std_logic;
        clk : IN std_logic;
        Q : OUT std_logic
        );
    END COMPONENT;

BEGIN       -- BEHAVIORAL

    Y<=UP_DW;
    Q <= Qaux;

    J(0) <= '1';
    K(0) <= '1';

    J(1) <= (not Qaux(3)) or (y and Qaux(2)) or (not (y) and Qaux(0));
    K(1) <=      Qaux(3)  or (y and Qaux(2)) or (not (y) and Qaux(0));

    J(2) <=      Qaux(3)  or (not (y) and not (Qaux(1))) or (y and Qaux(0));
    K(2) <= (not Qaux(3)) or (not (y) and not (Qaux(1))) or (y and Qaux(0));

    J(3) <= (not (y) and not (Qaux(1))) or (y and Qaux(2));
    K(3) <= (not (y) and not (Qaux(2))) or (y and Qaux(1));

    JK_0: FF_JK PORT MAP(
        J => J(0),
        K => K(0),
        clk => CLK_in,
        Q => Qaux(0)
    );

    JK_1: FF_JK PORT MAP(
        J =>  J(1),
        K => K(1),
        clk => CLK_in,
        Q => Qaux(1)
    );

    JK_2: FF_JK PORT MAP(
        J => J(2),
        K => K(2),
        clk => CLK_in,
        Q => Qaux(2)
    );

    JK_3: FF_JK PORT MAP(
        J => J(3),
        K => K(3),
        clk => CLK_in,
        Q => Qaux(3)
    );

end Behavioral;