LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Main IS
    PORT
    (
        A :  IN  STD_LOGIC;
        B :  IN  STD_LOGIC;
        C :  IN  STD_LOGIC;
        D :  IN  STD_LOGIC;
        CLK1 :  IN  STD_LOGIC;
        CLK2 :  IN  STD_LOGIC;
        CLRN :  IN  STD_LOGIC;
        LDN :  IN  STD_LOGIC;
        QA :  OUT  STD_LOGIC;
        QB :  OUT  STD_LOGIC;
        QC :  OUT  STD_LOGIC;
        QD :  OUT  STD_LOGIC
    );
END Main;

ARCHITECTURE bdf_type OF Main IS

SIGNAL  sig0 :  STD_LOGIC;
SIGNAL  sig1 :  STD_LOGIC;
SIGNAL  sig2 :  STD_LOGIC;
SIGNAL  sig3 :  STD_LOGIC;
SIGNAL  sig4 :  STD_LOGIC;
SIGNAL  sig5 :  STD_LOGIC;
SIGNAL  sig6 :  STD_LOGIC;
SIGNAL  sig7 :  STD_LOGIC;
SIGNAL  sig8 :  STD_LOGIC;

SIGNAL  sig9 :  STD_LOGIC;
SIGNAL  sig10 :  STD_LOGIC;
SIGNAL  sig11 :  STD_LOGIC;
SIGNAL  sig12 :  STD_LOGIC;

BEGIN
QA <= sig9;
QB <= sig10;
QC <= sig11;
QD <= sig12;

sig0 <= (NOT LDN OR NOT CLRN);
sig1 <= NOT(A AND sig0);
sig2 <= NOT(B AND sig0 AND CLRN);
sig3 <= NOT(C AND sig0 AND CLRN);
sig4 <= NOT(D AND sig0 AND CLRN);

sig5 <= NOT(not sig1 AND CLRN);
sig6 <= NOT(not sig2 AND CLRN);
sig7 <= NOT(not sig3 AND CLRN);
sig8 <= NOT(not sig4 AND CLRN);

process(CLK1,CLK2,sig0,sig1,sig2,sig3,sig4,sig5,sig6,sig7,sig8,sig9,sig10,sig11,sig12)
begin

if(rising_edge(CLK1)) then--dla A
    if((sig1='0') and (sig5='1')) then
        sig9 <= '0';
    elsif((sig1='1') and (sig5='0')) then
        sig9 <= '1';
    elsif((sig1='0') and (sig5='0')) then
        sig9 <= sig9;
    end if;
end if;


if(rising_edge(CLK2)) then--dla b
    if((sig2='0') and (sig6='1')) then
        sig10 <= '0';
    elsif((sig2='1') and (sig6='0')) then
        sig10 <= '1';
    elsif((sig2='0') and (sig6='0')) then
        sig10<= sig10;
    end if;
end if;

if(not(sig10='0')) then
    if((sig3='0') and (sig7='1')) then
        sig11 <= '0';
    elsif((sig3='1') and (sig7='0')) then
        sig11 <= '1';
    elsif((sig3='0') and (sig7='0')) then
        sig11 <=sig11;
    end if;
end if;
if(not(sig11='0')) then
    if((sig4='0') and (sig8='1')) then
        sig12 <= '0';
    elsif((sig4='1') and (sig8='0')) then
        sig12 <= '1';
    elsif((sig4='0') and (sig8='0')) then
        sig12 <= sig12;
    end if;
end if;


end process;


END bdf_type;


_____________________________________________________________________________________________________________________________________


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY TestBench74177 IS
END TestBench74177;

ARCHITECTURE behavior OF TestBench74177 IS

    COMPONENT Main
    PORT(
         CLK1 : IN  std_logic;
         A : IN  std_logic;
         B : IN  std_logic;
         C : IN  std_logic;
            D : IN  std_logic;
         CLK2 : IN  std_logic;
         CLRN : IN  std_logic;
         LDN : IN  std_logic;
         QA : OUT  std_logic;
         QB : OUT  std_logic;
         QC : OUT  std_logic;
         QD : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal CLK1 : std_logic := '0';
   signal A : std_logic := '0';
   signal B : std_logic := '0';
   signal C : std_logic := '0';
    signal D : std_logic := '0';
   signal CLK2 : std_logic := '0';
   signal CLRN : std_logic := '0';
   signal LDN : std_logic := '0';


    --Outputs
   signal QA : std_logic;
   signal QB : std_logic;
   signal QC : std_logic;
   signal QD : std_logic;

   -- Clock period definitions
   constant CLK1_period : time := 10 ns;
   constant CLK2_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: Main PORT MAP (
          CLK1 => CLK1,
          A => A,
          B => B,
          C => C,
             D => D,
          CLK2 => CLK2,
          CLRN => CLRN,
          LDN => LDN,
          QA => QA,
          QB => QB,
          QC => QC,
          QD => QD
        );

   -- Clock process definitions
   CLK1_process :process
   begin
        CLK1 <= '0';
        wait for CLK1_period/2;
        CLK1 <= '1';
        wait for CLK1_period/2;
   end process;

   CLK2_process :process
   begin
        CLK2 <= '0';
        wait for CLK2_period/2;
        CLK2 <= '1';
        wait for CLK2_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 50 ns;
      wait for CLK1_period*10;

      A <= '0';
        B <= '0';
        C <= '0';
        D <= '0';
        CLRN <= '1';
        LDN <= '0';
        wait for 50 ns;
        A <= '0';
        B <= '0';
        C <= '0';
        D <= '0';
        CLRN <= '1';
        LDN <= '1';

        wait for 50 ns;
        A <= '0';
        B <= '0';
        C <= '0';
        D <= '1';
        CLRN <= '1';
        LDN <= '0';
        wait for 50 ns;
        A <= '0';
        B <= '0';
        C <= '0';
        D <= '1';
        CLRN <= '1';
        LDN <= '1';
        wait for 50 ns;

        wait for 50 ns;
        A <= '0';
        B <= '0';
        C <= '1';
        D <= '0';
        CLRN <= '1';
        LDN <= '0';
        wait for 50 ns;
        A <= '0';
        B <= '0';
        C <= '1';
        D <= '0';
        CLRN <= '1';
        LDN <= '1';
        wait for 50 ns;
        A <= '0';
        B <= '0';
        C <= '1';
        D <= '0';
        CLRN <= '0';
        LDN <= '1';
        wait for 50 ns;





        A <= '0';
        B <= '0';
        C <= '0';
        D <= '0';
        CLRN <= '1';
        LDN <= '0';
        wait for 50 ns;
        A <= '0';
        B <= '0';
        C <= '0';
        D <= '1';
        wait for 50 ns;
        A <= '0';
        B <= '0';
        C <= '1';
        D <= '0';
        wait for 50 ns;
        A <= '0';
        B <= '0';
        C <= '1';
        D <= '1';
        wait for 50 ns;
        A <= '0';
        B <= '1';
        C <= '0';
        D <= '0';
        wait for 50 ns;
        A <= '0';
        B <= '1';
        C <= '0';
        D <= '1';
        wait for 50 ns;
        A <= '0';
        B <= '1';
        C <= '1';
        D <= '0';
        wait for 50 ns;
        A <= '0';
        B <= '1';
        C <= '1';
        D <= '1';
        wait for 50 ns;
        A <= '1';
        B <= '0';
        C <= '0';
        D <= '0';
        wait for 50 ns;
        A <= '1';
        B <= '0';
        C <= '0';
        D <= '1';
        wait for 50 ns;
        A <= '1';
        B <= '0';
        C <= '1';
        D <= '0';
        wait for 50 ns;
        A <= '1';
        B <= '0';
        C <= '1';
        D <= '1';
        wait for 50 ns;
        A <= '1';
        B <= '1';
        C <= '0';
        D <= '0';
        wait for 50 ns;
        A <= '1';
        B <= '1';
        C <= '0';
        D <= '1';
        wait for 50 ns;
        A <= '1';
        B <= '1';
        C <= '1';
        D <= '0';
        wait for 50 ns;
        A <= '1';
        B <= '1';
        C <= '1';
        D <= '1';
        wait for 50 ns;

      wait;
   end process;

END;