7Segment iterator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Main is
    Port(
        Clk : in STD_LOGIC;
        SevenSegment : out STD_LOGIC_VECTOR(7 downto 0);
        SevenSegmentEnable : out STD_LOGIC_VECTOR(2 downto 0);
        SevenSegmentDot : out STD_LOGIC;
        LED : out STD_LOGIC
    );
end Main;

architecture Behavioral of Main is
    --                                  268435456
    constant LICZNIK_LIMIT : integer := 100000000;
    signal licznik : unsigned(27 downto 0);

    signal eCnt : unsigned(2 downto 0);
    signal ses : STD_LOGIC_VECTOR(0 to 7) := "00000000";
    signal dot : STD_LOGIC;
begin
process(Clk)
begin
    if rising_edge(Clk) then
        if licznik = LICZNIK_LIMIT then
            licznik <= b"0000000000000000000000000000";
            eCnt <= eCnt + 1;
        else
            licznik <= licznik + 1;
        end if;
    end if;

    case eCnt is
        when "000" => ses <= "01111111"; dot <= '1';
        when "001" => ses <= "10111111"; dot <= '0';
        when "010" => ses <= "11011111"; dot <= '0';
        when "011" => ses <= "11101111"; dot <= '0';
        when "100" => ses <= "11110111"; dot <= '0';
        when "101" => ses <= "11111011"; dot <= '0';
        when "110" => ses <= "11111101"; dot <= '0';
        when "111" => ses <= "11111110"; dot <= '0';
        when others => ses <= "11111111"; dot <= '1';
    end case;
end process;

SevenSegment <= ses;
LED <= dot;
SevenSegmentEnable <= "000";
end Behavioral;