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-- Company:
-- Engineer:
--
-- Create Date:    09:20:29 10/18/2017
-- Design Name:
-- Module Name:    ALU_D - str_arch
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU_D is


port (Af : in  STD_LOGIC_VECTOR (3 downto 0);
           Bf : in  STD_LOGIC_VECTOR (3 downto 0);
           f0f : in  STD_LOGIC;
           f1f : in  STD_LOGIC;
           Yf : out  STD_LOGIC_VECTOR (4 downto 0));
              end ALU_D;
architecture str_arch of ALU_D is
component ALU
port (A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           f0 : in  STD_LOGIC;
           f1 : in  STD_LOGIC;
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
              end component;
component ALU2
 Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end component;

component ALU3
Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end component;
component MUX
Port ( i0 : in  STD_LOGIC_VECTOR (4 downto 0);
           i1 : in  STD_LOGIC_VECTOR (4 downto 0);
           i2 : in  STD_LOGIC_VECTOR (4 downto 0);
           i3 : in  STD_LOGIC_VECTOR (4 downto 0);
           f0 : in  STD_LOGIC;
           f1 : in  STD_LOGIC;
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end component;

signal p1,p2,p3 : 4 downto 0;

begin
unit1: ALU port map (A<=Af,B<=Bf,f0<=f0f,f1<=f1f,Y<=p1);
unit2: ALU2 port map (A<=Af,B<=Bf,Y<=p2);
unit3: ALU3 port map (A<=Af,B<=Bf,Y<=p3);
unit4: MUX port map (i0<=p1,i1<=p1,i2<=p2,i3<=p3,f0<=f0f,f1<=f1f,Y<=Yf);



end str_arch;