JK_LATCH

-------------------------------------------
-- AND Gate
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity vhdl_and_gate is
    Port ( INO1 : in  STD_LOGIC;    -- OR gate input
           INO2 : in  STD_LOGIC;    -- OR gate input
           OO : out  STD_LOGIC);    -- OR gate output
end vhdl_and_gate;

architecture vhdl_and_gate of vhdl_and_gate is
begin
OO <= not INO1 and not INO2;    -- 2 input OR gate
end vhdl_and_gate;
-------------------------------------------
-- up counter with async reset
-- uses signal

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity licznik is
generic (N:integer := 32);
    Port(
    C : in std_logic; -- clock signal input
    RST : in std_logic; --asynchronous reset, on low level
    data : out std_logic_vector(N-1 downto 0)
    );
end licznik;


architecture l1 of licznik is
signal a: std_logic_vector(N-1 downto 0);
begin

    process(RST,C)
        begin
            if (RST = '0') then
                a<= (others => '0');
            elsif (C'event and C='0') then -- on falling edge
                a <= a+1; -- increment
            end if;
        end process;
    data <= a;
end l1;
-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity latch_d is
    Port(
        D,C : in bit;
        Q : out bit
    );
end latch_d;

architecture a1 of latch_d is
begin
    process(C)
    begin
        if C'event and C='0' then Q <= not D;
        end if;
    end process;
end a1;

-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- jk latch with synchronous reset
entity jk_sr is
    port(J,K,C,R  :in bit; Q : out bit);
end jk_sr;

architecture jk3 of jk_sr is -- przerzutnik jk z synchronicznym resetem
begin
    process(C)
        variable ta: bit;
    begin
        if (C'event and C='1') then -- on clock input
            if R = '1' then ta := '0';
            else

                if J='1' and K='1' then -- toggle
                    ta := not ta;
                elsif J='0' and K='1' then -- reset
                    ta := '0';
                elsif J='1' and K='0' then -- set
                    ta := '1';
                else -- no change
                    ta := ta;
                end if;

            end if;
        end if;
        Q <= ta;
    end process;
end jk3;

-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- jk latch with asynchronous reset
entity jk_ar is
    port(J,K,C,R  :in bit; Q : out bit);
end jk_ar;

architecture jk2 of jk_ar is -- przerzutnik jk z asynchronicznym resetem
begin
    process(R,C)
        variable ta: bit;
    begin
        if R = '1' then ta := '0';
        else
            if (C'event and C='1') then -- on clock input
                if J='1' and K='1' then -- toggle
                    ta := not ta;
                elsif J='0' and K='1' then -- reset
                    ta := '0';
                elsif J='1' and K='0' then -- set
                    ta := '1';
                else -- no change
                    ta := ta;
                end if;
            end if;
        end if;
        Q <= ta;
    end process;
end jk2;


-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- jk latch
entity jk is
    port(J,K,C  :in bit; Q : out bit);
end jk;

architecture jk1 of jk is -- przerzutnik jk bez wejscia reset
begin
    process(C)
        variable ta: bit;
    begin
        if (C'event and C='1') then -- on clock input
            if J='1' and K='1' then -- toggle
                ta := not ta;
            elsif J='0' and K='1' then -- reset
                ta := '0';
            elsif J='1' and K='0' then -- set
                ta := '1';
            else -- no change
                ta := ta;
            end if;
        end if;
        Q <= ta;
    end process;
end jk1;