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Licznik ASK

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Mar 18th, 2019
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VHDL 4.59 KB | None | 0 0
  1. LIBRARY ieee;
  2. USE ieee.std_logic_1164.all;
  3. USE ieee.std_logic_arith.all;
  4. USE ieee.std_logic_unsigned.all;
  5.  
  6. ENTITY lab2 is
  7. port (
  8.     CLOCK_50: in std_logic;
  9.     HEX0 : out std_logic_vector (6 downto 0);
  10.     HEX1 : out std_logic_vector (6 downto 0);
  11.     HEX2 : out std_logic_vector (6 downto 0);
  12.     Q : out integer  range 0 to 9
  13.     );
  14. END lab2;
  15.  
  16.  
  17. ARCHITECTURE Behavioral of lab2 is
  18.     signal mhz: integer  range 0 to 50000000;
  19.     signal counter: integer  range 0 to 9;
  20.     signal counter1: integer  range 0 to 9;
  21.     signal counter2: integer  range 0 to 9;
  22.    
  23.     BEGIN PROCESS (CLOCK_50, mhz)
  24.     BEGIN
  25.         IF (CLOCK_50'EVENT AND CLOCK_50 = '1') THEN
  26.             mhz <= mhz+ 1;
  27.             IF (mhz = 49999999) THEN
  28.                 counter<=counter+1;
  29.                 IF (counter = 9) THEN
  30.                     counter<=0;
  31.                     counter1<=counter1+1;
  32.                     IF (counter1 = 9) THEN
  33.                         counter1<=0;
  34.                         counter2<=counter2+1;
  35.                         IF (counter2 = 9) THEN
  36.                         counter2<=0;       
  37.                         END IF;
  38.                     END IF;
  39.                 END IF;
  40.             END IF;
  41.         END IF;
  42.     END PROCESS;
  43.     PROCESS (CLOCK_50,counter)
  44.     BEGIN
  45.     CASE (counter) is
  46.                     when 0 => HEX0 <= "1000000";
  47.                     when 1 => HEX0 <= "1111001";
  48.                     when 2 => HEX0 <= "0100100";
  49.                     when 3 => HEX0 <= "0110000";
  50.                     when 4 => HEX0 <= "0011001";
  51.                     when 5 => HEX0 <= "0010010";
  52.                     when 6 => HEX0 <= "0000010";
  53.                     when 7 => HEX0 <= "1111000";
  54.                     when 8 => HEX0 <= "0000000";
  55.                     when 9 => HEX0 <= "0010000";
  56.                     when others => HEX0 <= "XXXXXXX";
  57.                 END CASE;
  58.     CASE (counter1) is
  59.                     when 0 => HEX1 <= "1000000";
  60.                     when 1 => HEX1 <= "1111001";
  61.                     when 2 => HEX1 <= "0100100";
  62.                     when 3 => HEX1 <= "0110000";
  63.                     when 4 => HEX1 <= "0011001";
  64.                     when 5 => HEX1 <= "0010010";
  65.                     when 6 => HEX1 <= "0000010";
  66.                     when 7 => HEX1 <= "1111000";
  67.                     when 8 => HEX1 <= "0000000";
  68.                     when 9 => HEX1 <= "0010000";
  69.                     when others => HEX1 <= "XXXXXXX";
  70.                 END CASE;
  71.     CASE (counter2) is
  72.                     when 0 => HEX2 <= "1000000";
  73.                     when 1 => HEX2 <= "1111001";
  74.                     when 2 => HEX2 <= "0100100";
  75.                     when 3 => HEX2 <= "0110000";
  76.                     when 4 => HEX2 <= "0011001";
  77.                     when 5 => HEX2 <= "0010010";
  78.                     when 6 => HEX2 <= "0000010";
  79.                     when 7 => HEX2 <= "1111000";
  80.                     when 8 => HEX2 <= "0000000";
  81.                     when 9 => HEX2 <= "0010000";
  82.                     when others => HEX2 <= "XXXXXXX";
  83.                 END CASE;
  84.  
  85.        
  86.     END PROCESS;
  87. END Behavioral;
  88. LIBRARY ieee;
  89. USE ieee.std_logic_1164.all;
  90. USE ieee.std_logic_arith.all;
  91. USE ieee.std_logic_unsigned.all;
  92.  
  93. ENTITY lab2 is
  94. port (
  95.     CLOCK_50: in std_logic;
  96.     HEX0 : out std_logic_vector (6 downto 0);
  97.     HEX1 : out std_logic_vector (6 downto 0);
  98.     HEX2 : out std_logic_vector (6 downto 0);
  99.     Q : out integer  range 0 to 9
  100.     );
  101. END lab2;
  102.  
  103.  
  104. ARCHITECTURE Behavioral of lab2 is
  105.     signal mhz: integer  range 0 to 50000000;
  106.     signal counter: integer  range 0 to 9;
  107.     signal counter1: integer  range 0 to 9;
  108.     signal counter2: integer  range 0 to 9;
  109.    
  110.     BEGIN PROCESS (CLOCK_50, mhz)
  111.     BEGIN
  112.         IF (CLOCK_50'EVENT AND CLOCK_50 = '1') THEN
  113.             mhz <= mhz+ 1;
  114.             IF (mhz = 49999999) THEN
  115.                 counter<=counter+1;
  116.                 IF (counter = 9) THEN
  117.                     counter<=0;
  118.                     counter1<=counter1+1;
  119.                     IF (counter1 = 9) THEN
  120.                         counter1<=0;
  121.                         counter2<=counter2+1;
  122.                         IF (counter2 = 9) THEN
  123.                         counter2<=0;       
  124.                         END IF;
  125.                     END IF;
  126.                 END IF;
  127.             END IF;
  128.         END IF;
  129.     END PROCESS;
  130.     PROCESS (CLOCK_50,counter)
  131.     BEGIN
  132.     CASE (counter) is
  133.                     when 0 => HEX0 <= "1000000";
  134.                     when 1 => HEX0 <= "1111001";
  135.                     when 2 => HEX0 <= "0100100";
  136.                     when 3 => HEX0 <= "0110000";
  137.                     when 4 => HEX0 <= "0011001";
  138.                     when 5 => HEX0 <= "0010010";
  139.                     when 6 => HEX0 <= "0000010";
  140.                     when 7 => HEX0 <= "1111000";
  141.                     when 8 => HEX0 <= "0000000";
  142.                     when 9 => HEX0 <= "0010000";
  143.                     when others => HEX0 <= "XXXXXXX";
  144.                 END CASE;
  145.     CASE (counter1) is
  146.                     when 0 => HEX1 <= "1000000";
  147.                     when 1 => HEX1 <= "1111001";
  148.                     when 2 => HEX1 <= "0100100";
  149.                     when 3 => HEX1 <= "0110000";
  150.                     when 4 => HEX1 <= "0011001";
  151.                     when 5 => HEX1 <= "0010010";
  152.                     when 6 => HEX1 <= "0000010";
  153.                     when 7 => HEX1 <= "1111000";
  154.                     when 8 => HEX1 <= "0000000";
  155.                     when 9 => HEX1 <= "0010000";
  156.                     when others => HEX1 <= "XXXXXXX";
  157.                 END CASE;
  158.     CASE (counter2) is
  159.                     when 0 => HEX2 <= "1000000";
  160.                     when 1 => HEX2 <= "1111001";
  161.                     when 2 => HEX2 <= "0100100";
  162.                     when 3 => HEX2 <= "0110000";
  163.                     when 4 => HEX2 <= "0011001";
  164.                     when 5 => HEX2 <= "0010010";
  165.                     when 6 => HEX2 <= "0000010";
  166.                     when 7 => HEX2 <= "1111000";
  167.                     when 8 => HEX2 <= "0000000";
  168.                     when 9 => HEX2 <= "0010000";
  169.                     when others => HEX2 <= "XXXXXXX";
  170.                 END CASE;
  171.  
  172.        
  173.     END PROCESS;
  174. END Behavioral;
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