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system_stm32f4xx.c (STM32F4-Discovery)

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  1. /**
  2.   ******************************************************************************
  3.   * @file    system_stm32f4xx.c
  4.   * @author  MCD Application Team
  5.   * @version V1.0.0
  6.   * @date    24-May-2013
  7.   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
  8.   *          This file contains the system clock configuration for STM32F4xx devices,
  9.   *          and is generated by the clock configuration tool
  10.   *          stm32f4xx_Clock_Configuration_V1.0.0.xls
  11.   *            
  12.   * 1.  This file provides two functions and one global variable to be called from
  13.   *     user application:
  14.   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  15.   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
  16.   *                      depending on the configuration made in the clock xls tool.
  17.   *                      This function is called at startup just after reset and
  18.   *                      before branch to main program. This call is made inside
  19.   *                      the "startup_stm32f4xx.s" file.
  20.   *
  21.   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  22.   *                                  by the user application to setup the SysTick
  23.   *                                  timer or configure other parameters.
  24.   *                                    
  25.   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  26.   *                                 be called whenever the core clock is changed
  27.   *                                 during program execution.
  28.   *
  29.   * 2. After each device reset the HSI (16 MHz) is used as system clock source.
  30.   *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
  31.   *    configure the system clock before to branch to main program.
  32.   *
  33.   * 3. If the system clock source selected by user fails to startup, the SystemInit()
  34.   *    function will do nothing and HSI still used as system clock source. User can
  35.   *    add some code to deal with this issue inside the SetSysClock() function.
  36.   *
  37.   * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
  38.   *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
  39.   *    through PLL, and you are using different crystal you have to adapt the HSE
  40.   *    value to your own configuration.
  41.   *
  42.   * 5. This file configures the system clock as follows:
  43.   *=============================================================================
  44.   *=============================================================================
  45.   *        Supported STM32F4xx device revision    | Rev A
  46.   *-----------------------------------------------------------------------------
  47.   *        System Clock source                    | PLL (HSE)
  48.   *-----------------------------------------------------------------------------
  49.   *        SYSCLK(Hz)                             | 168000000
  50.   *-----------------------------------------------------------------------------
  51.   *        HCLK(Hz)                               | 168000000
  52.   *-----------------------------------------------------------------------------
  53.   *        AHB Prescaler                          | 1
  54.   *-----------------------------------------------------------------------------
  55.   *        APB1 Prescaler                         | 8
  56.   *-----------------------------------------------------------------------------
  57.   *        APB2 Prescaler                         | 8
  58.   *-----------------------------------------------------------------------------
  59.   *        HSE Frequency(Hz)                      | 8000000
  60.   *-----------------------------------------------------------------------------
  61.   *        PLL_M                                  | 8
  62.   *-----------------------------------------------------------------------------
  63.   *        PLL_N                                  | 336
  64.   *-----------------------------------------------------------------------------
  65.   *        PLL_P                                  | 2
  66.   *-----------------------------------------------------------------------------
  67.   *        PLL_Q                                  | 7
  68.   *-----------------------------------------------------------------------------
  69.   *        PLLI2S_N                               | NA
  70.   *-----------------------------------------------------------------------------
  71.   *        PLLI2S_R                               | NA
  72.   *-----------------------------------------------------------------------------
  73.   *        I2S input clock                        | NA
  74.   *-----------------------------------------------------------------------------
  75.   *        VDD(V)                                 | 3.3
  76.   *-----------------------------------------------------------------------------
  77.   *        Main regulator output voltage          | Scale1 mode
  78.   *-----------------------------------------------------------------------------
  79.   *        Flash Latency(WS)                      | 5
  80.   *-----------------------------------------------------------------------------
  81.   *        Prefetch Buffer                        | OFF
  82.   *-----------------------------------------------------------------------------
  83.   *        Instruction cache                      | ON
  84.   *-----------------------------------------------------------------------------
  85.   *        Data cache                             | ON
  86.   *-----------------------------------------------------------------------------
  87.   *        Require 48MHz for USB OTG FS,          | Disabled
  88.   *        SDIO and RNG clock                     |
  89.   *-----------------------------------------------------------------------------
  90.   *=============================================================================
  91.   ******************************************************************************
  92.   * @attention
  93.   *
  94.   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  95.   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  96.   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  97.   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  98.   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  99.   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  100.   *
  101.   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  102.   ******************************************************************************
  103.   */
  104.  
  105. /** @addtogroup CMSIS
  106.   * @{
  107.   */
  108.  
  109. /** @addtogroup stm32f4xx_system
  110.   * @{
  111.   */  
  112.  
  113. /** @addtogroup STM32F4xx_System_Private_Includes
  114.   * @{
  115.   */
  116.  
  117. #include "stm32f4xx.h"
  118.  
  119. /**
  120.   * @}
  121.   */
  122.  
  123. /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
  124.   * @{
  125.   */
  126.  
  127. /**
  128.   * @}
  129.   */
  130.  
  131. /** @addtogroup STM32F4xx_System_Private_Defines
  132.   * @{
  133.   */
  134.  
  135. /************************* Miscellaneous Configuration ************************/
  136. /*!< Uncomment the following line if you need to use external SRAM mounted
  137.      on STM324xG_EVAL board as data memory  */
  138. /* #define DATA_IN_ExtSRAM */
  139.  
  140. /*!< Uncomment the following line if you need to relocate your vector Table in
  141.      Internal SRAM. */
  142. /* #define VECT_TAB_SRAM */
  143. #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
  144.                                    This value must be a multiple of 0x200. */
  145. /******************************************************************************/
  146.  
  147. /************************* PLL Parameters *************************************/
  148. /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
  149. #define PLL_M      8
  150. #define PLL_N      336
  151.  
  152. /* SYSCLK = PLL_VCO / PLL_P */
  153. #define PLL_P      2
  154.  
  155. /* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
  156. #define PLL_Q      7
  157.  
  158. /******************************************************************************/
  159.  
  160. /**
  161.   * @}
  162.   */
  163.  
  164. /** @addtogroup STM32F4xx_System_Private_Macros
  165.   * @{
  166.   */
  167.  
  168. /**
  169.   * @}
  170.   */
  171.  
  172. /** @addtogroup STM32F4xx_System_Private_Variables
  173.   * @{
  174.   */
  175.  
  176.   uint32_t SystemCoreClock = 168000000;
  177.  
  178.   __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  179.  
  180. /**
  181.   * @}
  182.   */
  183.  
  184. /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
  185.   * @{
  186.   */
  187.  
  188. static void SetSysClock(void);
  189. #ifdef DATA_IN_ExtSRAM
  190.   static void SystemInit_ExtMemCtl(void);
  191. #endif /* DATA_IN_ExtSRAM */
  192.  
  193. /**
  194.   * @}
  195.   */
  196.  
  197. /** @addtogroup STM32F4xx_System_Private_Functions
  198.   * @{
  199.   */
  200.  
  201. /**
  202.   * @brief  Setup the microcontroller system
  203.   *         Initialize the Embedded Flash Interface, the PLL and update the
  204.   *         SystemFrequency variable.
  205.   * @param  None
  206.   * @retval None
  207.   */
  208. void SystemInit(void)
  209. {
  210.   /* FPU settings ------------------------------------------------------------*/
  211.   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  212.     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
  213.   #endif
  214.   /* Reset the RCC clock configuration to the default reset state ------------*/
  215.   /* Set HSION bit */
  216.   RCC->CR |= (uint32_t)0x00000001;
  217.  
  218.   /* Reset CFGR register */
  219.   RCC->CFGR = 0x00000000;
  220.  
  221.   /* Reset HSEON, CSSON and PLLON bits */
  222.   RCC->CR &= (uint32_t)0xFEF6FFFF;
  223.  
  224.   /* Reset PLLCFGR register */
  225.   RCC->PLLCFGR = 0x24003010;
  226.  
  227.   /* Reset HSEBYP bit */
  228.   RCC->CR &= (uint32_t)0xFFFBFFFF;
  229.  
  230.   /* Disable all interrupts */
  231.   RCC->CIR = 0x00000000;
  232.  
  233. #ifdef DATA_IN_ExtSRAM
  234.   SystemInit_ExtMemCtl();
  235. #endif /* DATA_IN_ExtSRAM */
  236.          
  237.   /* Configure the System clock source, PLL Multiplier and Divider factors,
  238.      AHB/APBx prescalers and Flash settings ----------------------------------*/
  239.   SetSysClock();
  240.  
  241.   /* Configure the Vector Table location add offset address ------------------*/
  242. #ifdef VECT_TAB_SRAM
  243.   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
  244. #else
  245.   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
  246. #endif
  247. }
  248.  
  249. /**
  250.    * @brief  Update SystemCoreClock variable according to Clock Register Values.
  251.   *         The SystemCoreClock variable contains the core clock (HCLK), it can
  252.   *         be used by the user application to setup the SysTick timer or configure
  253.   *         other parameters.
  254.   *          
  255.   * @note   Each time the core clock (HCLK) changes, this function must be called
  256.   *         to update SystemCoreClock variable value. Otherwise, any configuration
  257.   *         based on this variable will be incorrect.        
  258.   *    
  259.   * @note   - The system frequency computed by this function is not the real
  260.   *           frequency in the chip. It is calculated based on the predefined
  261.   *           constant and the selected clock source:
  262.   *            
  263.   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  264.   *                                              
  265.   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  266.   *                          
  267.   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
  268.   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
  269.   *        
  270.   *         (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
  271.   *             16 MHz) but the real value may vary depending on the variations
  272.   *             in voltage and temperature.  
  273.   *    
  274.   *         (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
  275.   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
  276.   *              frequency of the crystal used. Otherwise, this function may
  277.   *              have wrong result.
  278.   *                
  279.   *         - The result of this function could be not correct when using fractional
  280.   *           value for HSE crystal.
  281.   *    
  282.   * @param  None
  283.   * @retval None
  284.   */
  285. void SystemCoreClockUpdate(void)
  286. {
  287.   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
  288.  
  289.   /* Get SYSCLK source -------------------------------------------------------*/
  290.   tmp = RCC->CFGR & RCC_CFGR_SWS;
  291.  
  292.   switch (tmp)
  293.   {
  294.     case 0x00:  /* HSI used as system clock source */
  295.       SystemCoreClock = HSI_VALUE;
  296.       break;
  297.     case 0x04:  /* HSE used as system clock source */
  298.       SystemCoreClock = HSE_VALUE;
  299.       break;
  300.     case 0x08:  /* PLL used as system clock source */
  301.  
  302.       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
  303.          SYSCLK = PLL_VCO / PLL_P
  304.          */    
  305.       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
  306.       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
  307.      
  308.       if (pllsource != 0)
  309.       {
  310.         /* HSE used as PLL clock source */
  311.         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
  312.       }
  313.       else
  314.       {
  315.         /* HSI used as PLL clock source */
  316.         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
  317.       }
  318.  
  319.       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
  320.       SystemCoreClock = pllvco/pllp;
  321.       break;
  322.     default:
  323.       SystemCoreClock = HSI_VALUE;
  324.       break;
  325.   }
  326.   /* Compute HCLK frequency --------------------------------------------------*/
  327.   /* Get HCLK prescaler */
  328.   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
  329.   /* HCLK frequency */
  330.   SystemCoreClock >>= tmp;
  331. }
  332.  
  333. /**
  334.   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
  335.   *         AHB/APBx prescalers and Flash settings
  336.   * @Note   This function should be called only once the RCC clock configuration  
  337.   *         is reset to the default reset state (done in SystemInit() function).  
  338.   * @param  None
  339.   * @retval None
  340.   */
  341. static void SetSysClock(void)
  342. {
  343. /******************************************************************************/
  344. /*            PLL (clocked by HSE) used as System clock source                */
  345. /******************************************************************************/
  346.   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  347.  
  348.   /* Enable HSE */
  349.   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
  350.  
  351.   /* Wait till HSE is ready and if Time out is reached exit */
  352.   do
  353.   {
  354.     HSEStatus = RCC->CR & RCC_CR_HSERDY;
  355.     StartUpCounter++;
  356.   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  357.  
  358.   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  359.   {
  360.     HSEStatus = (uint32_t)0x01;
  361.   }
  362.   else
  363.   {
  364.     HSEStatus = (uint32_t)0x00;
  365.   }
  366.  
  367.   if (HSEStatus == (uint32_t)0x01)
  368.   {
  369.     /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
  370.     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
  371.     PWR->CR |= PWR_CR_VOS;
  372.  
  373.     /* HCLK = SYSCLK / 1*/
  374.     RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
  375.      
  376.     /* PCLK2 = HCLK / 8*/
  377.     RCC->CFGR |= RCC_CFGR_PPRE2_DIV8;
  378.    
  379.     /* PCLK1 = HCLK / 8*/
  380.     RCC->CFGR |= RCC_CFGR_PPRE1_DIV8;
  381.  
  382.     /* Configure the main PLL */
  383.     RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
  384.                    (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
  385.  
  386.     /* Enable the main PLL */
  387.     RCC->CR |= RCC_CR_PLLON;
  388.  
  389.     /* Wait till the main PLL is ready */
  390.     while((RCC->CR & RCC_CR_PLLRDY) == 0)
  391.     {
  392.     }
  393.    
  394.     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
  395.     FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
  396.  
  397.     /* Select the main PLL as system clock source */
  398.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
  399.     RCC->CFGR |= RCC_CFGR_SW_PLL;
  400.  
  401.     /* Wait till the main PLL is used as system clock source */
  402.     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
  403.     {
  404.     }
  405.   }
  406.   else
  407.   { /* If HSE fails to start-up, the application will have wrong clock
  408.          configuration. User can add here some code to deal with this error */
  409.   }
  410.  
  411. }
  412.  
  413. /**
  414.   * @brief  Setup the external memory controller. Called in startup_stm32f4xx.s
  415.   *          before jump to __main
  416.   * @param  None
  417.   * @retval None
  418.   */
  419. #ifdef DATA_IN_ExtSRAM
  420. /**
  421.   * @brief  Setup the external memory controller.
  422.   *         Called in startup_stm32f4xx.s before jump to main.
  423.   *         This function configures the external SRAM mounted on STM324xG_EVAL board
  424.   *         This SRAM will be used as program data memory (including heap and stack).
  425.   * @param  None
  426.   * @retval None
  427.   */
  428. void SystemInit_ExtMemCtl(void)
  429. {
  430. /*-- GPIOs Configuration -----------------------------------------------------*/
  431. /*
  432.  +-------------------+--------------------+------------------+------------------+
  433.  +                       SRAM pins assignment                                   +
  434.  +-------------------+--------------------+------------------+------------------+
  435.  | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
  436.  | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
  437.  | PD4  <-> FSMC_NOE | PE3  <-> FSMC_A19  | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
  438.  | PD5  <-> FSMC_NWE | PE4  <-> FSMC_A20  | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
  439.  | PD8  <-> FSMC_D13 | PE7  <-> FSMC_D4   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
  440.  | PD9  <-> FSMC_D14 | PE8  <-> FSMC_D5   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
  441.  | PD10 <-> FSMC_D15 | PE9  <-> FSMC_D6   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
  442.  | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7   | PF13 <-> FSMC_A7 |------------------+
  443.  | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8   | PF14 <-> FSMC_A8 |
  444.  | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9   | PF15 <-> FSMC_A9 |
  445.  | PD14 <-> FSMC_D0  | PE13 <-> FSMC_D10  |------------------+
  446.  | PD15 <-> FSMC_D1  | PE14 <-> FSMC_D11  |
  447.  |                   | PE15 <-> FSMC_D12  |
  448.  +-------------------+--------------------+
  449. */
  450.    /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
  451.   RCC->AHB1ENR   = 0x00000078;
  452.  
  453.   /* Connect PDx pins to FSMC Alternate function */
  454.   GPIOD->AFR[0]  = 0x00cc00cc;
  455.   GPIOD->AFR[1]  = 0xcc0ccccc;
  456.   /* Configure PDx pins in Alternate function mode */  
  457.   GPIOD->MODER   = 0xaaaa0a0a;
  458.   /* Configure PDx pins speed to 100 MHz */  
  459.   GPIOD->OSPEEDR = 0xffff0f0f;
  460.   /* Configure PDx pins Output type to push-pull */  
  461.   GPIOD->OTYPER  = 0x00000000;
  462.   /* No pull-up, pull-down for PDx pins */
  463.   GPIOD->PUPDR   = 0x00000000;
  464.  
  465.   /* Connect PEx pins to FSMC Alternate function */
  466.   GPIOE->AFR[0]  = 0xc00cc0cc;
  467.   GPIOE->AFR[1]  = 0xcccccccc;
  468.   /* Configure PEx pins in Alternate function mode */
  469.   GPIOE->MODER   = 0xaaaa828a;
  470.   /* Configure PEx pins speed to 100 MHz */
  471.   GPIOE->OSPEEDR = 0xffffc3cf;
  472.   /* Configure PEx pins Output type to push-pull */  
  473.   GPIOE->OTYPER  = 0x00000000;
  474.   /* No pull-up, pull-down for PEx pins */
  475.   GPIOE->PUPDR   = 0x00000000;
  476.  
  477.   /* Connect PFx pins to FSMC Alternate function */
  478.   GPIOF->AFR[0]  = 0x00cccccc;
  479.   GPIOF->AFR[1]  = 0xcccc0000;
  480.   /* Configure PFx pins in Alternate function mode */  
  481.   GPIOF->MODER   = 0xaa000aaa;
  482.   /* Configure PFx pins speed to 100 MHz */
  483.   GPIOF->OSPEEDR = 0xff000fff;
  484.   /* Configure PFx pins Output type to push-pull */  
  485.   GPIOF->OTYPER  = 0x00000000;
  486.   /* No pull-up, pull-down for PFx pins */
  487.   GPIOF->PUPDR   = 0x00000000;
  488.  
  489.   /* Connect PGx pins to FSMC Alternate function */
  490.   GPIOG->AFR[0]  = 0x00cccccc;
  491.   GPIOG->AFR[1]  = 0x000000c0;
  492.   /* Configure PGx pins in Alternate function mode */
  493.   GPIOG->MODER   = 0x00080aaa;
  494.   /* Configure PGx pins speed to 100 MHz */
  495.   GPIOG->OSPEEDR = 0x000c0fff;
  496.   /* Configure PGx pins Output type to push-pull */  
  497.   GPIOG->OTYPER  = 0x00000000;
  498.   /* No pull-up, pull-down for PGx pins */
  499.   GPIOG->PUPDR   = 0x00000000;
  500.  
  501. /*-- FSMC Configuration ------------------------------------------------------*/
  502.   /* Enable the FSMC interface clock */
  503.   RCC->AHB3ENR         = 0x00000001;
  504.  
  505.   /* Configure and enable Bank1_SRAM2 */
  506.   FSMC_Bank1->BTCR[2]  = 0x00001015;
  507.   FSMC_Bank1->BTCR[3]  = 0x00010603;
  508.   FSMC_Bank1E->BWTR[2] = 0x0fffffff;
  509.  /*
  510.   Bank1_SRAM2 is configured as follow:
  511.  
  512.   p.FSMC_AddressSetupTime = 3;
  513.   p.FSMC_AddressHoldTime = 0;
  514.   p.FSMC_DataSetupTime = 6;
  515.   p.FSMC_BusTurnAroundDuration = 1;
  516.   p.FSMC_CLKDivision = 0;
  517.   p.FSMC_DataLatency = 0;
  518.   p.FSMC_AccessMode = FSMC_AccessMode_A;
  519.  
  520.   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
  521.   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
  522.   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
  523.   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
  524.   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
  525.   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
  526.   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
  527.   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
  528.   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
  529.   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
  530.   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
  531.   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
  532.   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
  533.   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
  534.   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
  535. */  
  536. }
  537. #endif /* DATA_IN_ExtSRAM */
  538.  
  539.  
  540. /**
  541.   * @}
  542.   */
  543.  
  544. /**
  545.   * @}
  546.   */
  547.  
  548. /**
  549.   * @}
  550.   */    
  551. /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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