20141002_KUAS_Verilog_Design_5Bit

/*******************************************/
/** 20141002 5-Bit Design (Use Data Flow) **/
/** Maker  : Yan                          **/
/** E-Mail : [email protected]        **/
/** Date   : 2014/10/02 pm.10:55          **/
/*******************************************/

module Design_5Bit(select, input1, input2, output1);
    input       [3:0]       select, input1, input2;
    output reg  [4:0]       output1;

    always@(input1)
    begin
        case(select)
            4'b1101 : output1 = ~(input1 & input2);
            4'b1100 : output1 = (input1 ~^ input2);
            4'b0111 : output1 = input1 / 2;
            4'b0101 : output1 = input1 * 2;
            4'b0001 : output1 = (input1 > input2) ? input1 : input2;
            4'b0000 : output1 = (input1 > input2) ? 5'b11111 : 5'b00000;
            default : output1 = 5'b01001;
        endcase
    end
endmodule