entity led_driver is
    generic (ROW_BYTES : integer := 32);

    port (
        rst_in  : in  STD_LOGIC;                     -- reset
        clk_in  : in  STD_LOGIC;                     -- input clock

        -- TODO memory interface

        -- SPI writer interface
        spi_data_out : out  STD_LOGIC_VECTOR(8 downto 0); -- output data
        spi_we_out   : out  STD_LOGIC;                    -- write enable
        spi_rdy_in   : in   STD_LOGIC;                    -- ready signal

        row_out      : out STD_LOGIC_VECTOR(1 downto 0);  -- active row counter
    );
end led_driver;

architecture Behaviour of led_driver is
    type state_t is (
        st_init,  -- initial state
        st_fetch_data,
        st_spi_wait,
        st_spi_push,
        st_next
    );

    signal state : state_t := st_init;
begin

            -- 1. fetch the next byte from the memory
            -- 2. wait until SPI became ready
            -- 3. push the data to the SPI writer
            -- 4. increment the counters

    process (clk_in, rst_in)
        variable current_row : integer from 0 to 3 := 0; -- current row
        variable current_byte : integer from 0 to ROW_BYTES-1;
    begin
        if rst_in = '1' then
            -- reset the device
            current_row := 0;
            current_byte := 0;
            spi_we_out <= '0';
            spi_data_out <= (others => '0');
            row_out <= "00";
            state <= st_init

        elsif clk_in'event and clk_in = '1' then
            spi_we_out <= '0';

            case state is
                when st_init =>
                    current_row := 0;
                    current_byte := 0;
                    row_out <= "00";
                    state <= st_fetch_data;

                when st_fetch_data =>
                    -- TODO read data from the memory
                    state <= st_spi_push;

                when st_spi_push =>
                    -- spi_data_out <= buffer(current_byte);
                    spi_we_out <= '1';
                    state <= st_spi_wait;

                when st_spi_wait =>
                    if spi_rdy_in = '1' then
                        state <= st_next;
                    end if;

                -- when st_next =>
                    -- incrementing counters

            end case;
        end if;
    end process;

end Behaviour;