entity VERKEERD is
port(   A,B : in integer range 0 to 3;
    Z : out std_logic_vector (3 downto 0));
end VERKEERD;

architecture TROEP of VERKEERD is
    SLECHT : process (A,B)
        begin
            Z <= `´0000´´;
            if (A = 0) then
                Z <= `´0011´´;
            elsif (A = 2) then
                Z <= `´1111´´;
            else
                case B is
                    when 0 =>
                        Z <= `´0000´´;
                    when 0 to 2 =>
                        Z <= `´1111´´;
                end case;
            end if;
        end SLECHT;
end TROEP;