-- here is our clock enable module.  We will take the incoming clock, lets say 100mhz and
-- only enable once a second lets say.  So we want a single pulse once a second to enable
-- the clock for a 1hz equivalent speed.  This is important to do since the hardware inside
-- of the FPGA expects this - you don't want to piss off the hardware *insert spooky music*
entity clockEnable is
    PORT (
        clk : in STD_LOGIC;         -- input clock
        clk_en : out STD_LOGIC;         -- output clock enable, a pulse
                            --   one clock period wide
        by : in integer range 0 to 100000000    -- our division value
    );
end clockEnable ;

architecture Behavioral of clockEnable is
    -- this will hold the count for the number of clocks that have gone by since the
    -- last clock enable pulse
    signal count: integer range 0 to 100000000;
begin

    -- our primary process where the pulse will be generated.
    process( clk )
    being
        if( rising_edge( clk ) ) then
            -- every 'by' clocks pulse.
            if( count = by ) then
                clk_en <= '1';
            else
                clk_en <= '0';
            end if;
        end if;
    end process;

end Behavioral; -- all done!

-- we are going to make a 4 LED knightrider pattern - i don't know if you know what
-- knightrider is so here is a youtube link: http://www.youtube.com/watch?v=Mo8Qls0HnWo
entity funLogicStuff is
    PORT (
        clk : in STD_LOGIC;             -- input clock
        clk_en : in STD_LOGIC;              -- input clock enable
        leds : out STD_LOGIC_VECTOR(3 downto 0)     -- output LED's
    );
end clockEnable ;

architecture Behavioral of clockEnable is
    signal led_reg: std_logic_vector(3 downto 0);
begin

    -- so this is a pretty big gotcha from the perspective of FPGA's.  the signal 'leds'
    -- is an output, there for we can not read it.  So we use a 'temporary' signal and
    -- read from that.  We will then take that 'temporary' signal and pass it out to
    -- the outside world!
    leds <= led_reg;

    -- our primary process
    process( clk )
    being
        -- the process is going to get clocked off of the main clock
        if( rising_edge( clk ) ) then
            -- this is VERY important.  We call them defaults - they are the default value
            -- that EVERY signal in the process should have.  So, you may have a situation
            -- where a signal is not changed on a clock tick, you still need to make sure
            -- that the value is assigned.  that is there should always be a default, or
            -- every IF should have an ELSE
            led_reg <= led_reg; -- we do this so the contents do not change if we are not
                                -- on a clock enable tick

            -- however we are only going to do anything unless we see a clock
            -- enable pulse.  in our case, once a second.
            if( clk_en = '1' ) then
                case led_reg is
                    when "0000" =>
                        led_reg <= "0001";
                    when "0001" =>
                        led_reg <= "0010";
                    when "0010" =>
                        led_reg <= "0100";
                    when "0100" =>
                        led_reg <= "1000";
                    when "1000" =>
                        led_reg <= "0001";
                    when others => null
                end case;
            end if;
        end if;
    end process;

end Behavioral;

entity topLevel is
    PORT (
        clk : in STD_LOGIC;                         -- input clock
        leds : out STD_LOGIC_VECTOR(3 downto 0)     -- output LED's
    );
end topLevel ;

architecture Behavioral of topLevel is

    component clockEnable
        PORT (
            clk : in std_logic;
            clk_en : out std_logic;
            by : in integer range 0 to 100000000
        );
    end component;

    component funLogicStuff
        PORT (
            clk : in std_logic;
            clk_en : in std_logic;
            leds : out std_logic_vector(3 downto 0)
        );
    end component;

    -- our generated clock enable signal that needs to be brought from
    -- our clock generator to our funlogicstuff module.
    signal clk_en : std_logic := '0';

begin

    Inst_clockEnable clockEnable port map(
        clk => clk, -- system clock
        clk_en => clk_en, -- our clock enable output
        by => 100000000 -- out constant that defines our clk en rate
    );

    Inst_funLogicStuff funLogicStuff port map(
        clk => clk, -- system clock
        clk_en => clk_en, -- note connected as input here
        leds => leds -- to the outside world!
    );

end Behavioral