library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
entity koder is
port(
      clk : in STD_LOGIC;
      dintabl : in integer := 0;
      din : in std_logic);
end koder;

architecture Behavioral of koder is

TYPE STATE_TYPE IS (s0,s1,s2,s3);
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;

component peremezh is
    Port (clk : in std_logic;
          din : in std_logic;
          dintabl : in integer := 0;
          dout : out std_logic_vector(999 downto 0));
end component;

signal address : integer := 0;
signal glavniyschetchik : integer := 0;
signal check1 : integer := 0;
signal peremezhdin : std_logic_vector(999 downto 0):=(others => '0');
signal rst : std_logic := '0';
signal findout: std_logic:='0';
signal findoutvspom: std_logic := '0';

type rom is array (0 to 2) of std_logic;
signal soderzhimoe2sost : rom := (others=> '0');
signal soderzhimoe3sost : rom := (others=> '0');
----------------------------------------------------------------------------
begin

clocked_proc : PROCESS (clk) BEGIN
    IF rising_edge(clk) THEN
        iF (rst = '1') THEN
            current_state <= s0;
        ELSE
            current_state <= next_state;
        END IF;
    END IF;
 END PROCESS clocked_proc;
 --------------------------------------------------------------------------
 nextstate_proc : PROCESS (clk,check1, glavniyschetchik, current_state) BEGIN
    CASE current_state IS
        WHEN s0 =>
                IF (check1=1) THEN
                next_state <= s1;
            END IF;
        WHEN s1 =>
            IF (check1=2) THEN
                next_state <= s2;
            END IF;
        WHEN s2 =>
            IF (check1=3) THEN
                next_state <= s3;
            end if;
        WHEN s3 =>
            IF (check1=4) THEN
                next_state <= s0;
            end if;
    END CASE;
  END PROCESS nextstate_proc;
 --------------------------------------------------------------
 output_proc : PROCESS (clk, current_state) BEGIN

  CASE current_state IS
  WHEN s0 =>

  WHEN s1 =>
        if rising_edge(clk) then
             findout <= din;
        end if;
  WHEN s2 =>
        if rising_edge(clk) then
              soderzhimoe2sost(1) <= soderzhimoe2sost(0);
              soderzhimoe2sost(0) <= din xor (soderzhimoe2sost(1) xor soderzhimoe2sost(2));
              soderzhimoe2sost(2) <= soderzhimoe2sost(1);
              findout <= soderzhimoe2sost(0) xor soderzhimoe2sost(2);

              soderzhimoe3sost(1) <= soderzhimoe3sost(0);
              soderzhimoe3sost(0) <= peremezhdin(address) xor (soderzhimoe3sost(1) xor soderzhimoe3sost(2));
              soderzhimoe3sost(2) <= soderzhimoe3sost(1);
              findoutvspom <= soderzhimoe3sost(0) xor soderzhimoe3sost(2);
      end if;
  WHEN s3 =>
        if rising_edge(clk) then
              soderzhimoe3sost(1) <= soderzhimoe3sost(0);
              soderzhimoe3sost(0) <= peremezhdin(address) xor (soderzhimoe3sost(1) xor soderzhimoe3sost(2));
              soderzhimoe3sost(2) <= soderzhimoe3sost(1);
              findout <= soderzhimoe3sost(0) xor soderzhimoe3sost(2);
        end if;
  END CASE;
  END PROCESS output_proc;

-----------------------------------------------------------------
schet_a: process(clk) begin
    if rising_edge(clk) then
        if address = 999 then
            address <= 0;
        else
            address <= address + 1;
        end if;
    end if;
end process;

schet_b: process(clk) begin
    if rising_edge(clk) then
        if glavniyschetchik = 5000 then
            glavniyschetchik <= 0;
        elsif glavniyschetchik = 999 then                       -- нулевое сост
            check1 <= check1 + 1;
            glavniyschetchik <= glavniyschetchik + 1;
        elsif glavniyschetchik = 1998 then                      -- первое сост
            check1 <= check1 + 1;
            glavniyschetchik <= glavniyschetchik + 1;
        elsif glavniyschetchik = 2997 then                      -- второе сост
            check1 <= check1 + 1;
            glavniyschetchik <= glavniyschetchik + 1;
        elsif glavniyschetchik = 3996 then                      -- третье сост
            check1 <= check1 + 1;
            glavniyschetchik <= glavniyschetchik + 1;
        else
            glavniyschetchik <= glavniyschetchik + 1;
        end if;
    end if;
end process;

komp: peremezh
port map(
    clk => clk,
    din => din,
    dintabl => dintabl,
    dout => peremezhdin);

end behavioral;