uas_arduino

Sigma Delta Test - Working @ Low Freq

May 15th, 2014
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use ieee.numeric_std.all;
  4.  
  5. library unisim;
  6. use unisim.vcomponents.all;
  7.  
  8. entity SigmaDelta is
  9.     Port ( clk : in  STD_LOGIC;
  10.             clk_out : out std_logic;
  11.            rst : in  STD_LOGIC;
  12.            diff_n : in  STD_LOGIC;
  13.            diff_p : in  STD_LOGIC;
  14.            o : out  STD_LOGIC;
  15.               leds : out std_logic_vector(7 downto 0);
  16.               dac : out std_logic_vector(7 downto 0));
  17. end SigmaDelta;
  18.  
  19. architecture Behavioral of SigmaDelta is
  20. --  signal max_count : integer := 256;
  21.     signal o_buf : std_logic;
  22.     signal total : unsigned(10 downto 0) := (others => '0');
  23.     signal count : unsigned(31 downto 0) := (others => '0');
  24.     signal fast_clk : std_logic := '0';
  25.     signal clk_buffer : std_logic := '0';
  26.     component mult
  27. port
  28.  (-- Clock in ports
  29.   CLK_IN1           : in     std_logic;
  30.   -- Clock out ports
  31.   CLK_OUT1          : out    std_logic
  32.  );
  33. end component;
  34. begin
  35.     clk_out <= clk_buffer;
  36.     ibufds_inst : IBUFDS
  37.     generic map (
  38.         IOSTANDARD => "LVDS_25"
  39.     )
  40.     port map (
  41.         O => o_buf,
  42.         I => diff_p,
  43.         IB => diff_n
  44.     );
  45.    
  46. --  your_instance_name : mult
  47. --  port map
  48. --   (-- Clock in ports
  49. --    CLK_IN1 => clk,
  50. --    -- Clock out ports
  51. --    CLK_OUT1 => fast_clk);
  52.    
  53. --  process(clk, rst)
  54. --      variable counter : unsigned(31 downto 0) := (others => '0');
  55. --      type lut_type is array (0 to 255) of integer range 0 to 255;
  56. --      variable lut : lut_type := (127,130,133,136,139,142,145,148,151,154,157,160,163,166,169,172,175,178,181,184,186,189,192,194,197,200,202,205,207,209,212,214,216,218,221,223,225,227,229,230,232,234,235,237,239,240,241,243,244,245,246,247,248,249,250,250,251,252,252,253,253,253,253,253,254,253,253,253,253,253,252,252,251,250,250,249,248,247,246,245,244,243,241,240,239,237,235,234,232,230,229,227,225,223,221,218,216,214,212,209,207,205,202,200,197,194,192,189,186,184,181,178,175,172,169,166,163,160,157,154,151,148,145,142,139,136,133,130,127,123,120,117,114,111,108,105,102,99,96,93,90,87,84,81,78,75,72,69,67,64,61,59,56,53,51,48,46,44,41,39,37,35,32,30,28,26,24,23,21,19,18,16,14,13,12,10,9,8,7,6,5,4,3,3,2,1,1,0,0,0,0,0,0,0,0,0,0,0,1,1,2,3,3,4,5,6,7,8,9,10,12,13,14,16,18,19,21,23,24,26,28,30,32,35,37,39,41,44,46,48,51,53,56,59,61,64,67,69,72,75,78,81,84,87,90,93,96,99,102,105,108,111,114,117,120,123);
  57. --      variable lut_pos : unsigned(7 downto 0) := (others => '0');
  58. --  begin
  59. --      if(rst = '0') then
  60. --          counter := (others => '0');
  61. --          lut_pos := (others => '0');
  62. --      elsif(rising_edge(clk)) then
  63. --          if(counter = 50000000/6400) then
  64. --              dac <= std_logic_vector(to_unsigned(lut(to_integer(lut_pos)), 8));
  65. --              lut_pos := lut_pos + 1;
  66. --              counter := (others => '0');
  67. --          else
  68. --              counter := counter + 1;
  69. --          end if;
  70. --      end if;
  71. --  end process;
  72.    
  73.    
  74.     process(clk, rst)
  75.         variable counter : unsigned(31 downto 0) := (others => '0');
  76.     begin
  77.         if(rst = '0') then
  78.             counter := (others => '0');
  79.             count <= (others => '0');
  80.             total <= (others => '0');
  81.             leds <= (others => '0');
  82.         elsif(rising_edge(clk)) then
  83.             if(counter = 1) then
  84.                 counter := (others => '0');
  85.                 clk_buffer <= not clk_buffer;
  86.                 o <= o_buf;
  87.                 if(o_buf = '1') then
  88.                     total <= total + 1;
  89.                 end if;
  90.                 if(count = 100000000/(44000*64)) then
  91.                     leds <= std_logic_vector(total(7 downto 0));
  92.                     total <= (others => '0');
  93.                     count <= (others => '0');
  94.                     dac <= std_logic_vector(total(7 downto 0));
  95.                 else
  96.                     count <= count + 1;
  97.                 end if;
  98.             else
  99.                 counter := counter + 1;
  100.             end if;
  101.         end if;
  102.     end process;
  103.  
  104. end Behavioral;
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