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Andruwkoo

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Dec 1st, 2018
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VHDL 0.71 KB | None | 0 0
  1. library IEEE;
  2.  
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity buzz is
  8.     port (
  9.         clock : in std_logic;
  10.         a     : out std_logic
  11.     );
  12. end buzz;
  13.  
  14. architecture Behavioral of buzz is
  15.  
  16. begin
  17.  
  18.     process(clock)
  19.         variable i : integer := 0;
  20.     begin
  21.         if clock'event and clock = '1' then
  22.             if i <= 50000000 then
  23.                 i := i + 1;
  24.                 a <= '1';
  25.             elsif i > 50000000 and i < 100000000 then
  26.                 i := i + 1;
  27.                 a <= '0';
  28.             elsif i = 100000000 then
  29.                 i := 0;
  30.             end if;
  31.         end if;
  32.     end process;
  33.  
  34. end Behavioral;
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