library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY fsm IS
port (  reset: in std_logic;
    clk: in std_logic;
    w, c, r: in std_logic;
    enable: out std_logic_vector(0 to 1);
    licz, drive, creset: out std_logic);
END ENTITY fsm;

--
ARCHITECTURE z12 OF fsm IS

type stany is (idle, read, write1, write2, compare);
signal state, next_state : stany;
signal req: std_logic_vector(2 downto 0);

BEGIN

synchrP: process (clk, reset)
begin
    if reset='0' then
        state <= idle;
    elsif (rising_edge(clk)) then
        state<= next_state;
    end if;
end process;

req <= w&c&r;

kombP: process(state, req)
begin

case state is
when idle =>
    if (req="100") then
        next_state <= write1; enable <= "10"; licz<='0'; drive <= '0'; creset <='0';
    elsif (req="010") then
        next_state <= compare; enable<="00"; licz<='1'; drive <= '0'; creset <='0';
    elsif (req="001") then
        next_state <= read; enable<="00"; licz<='0'; drive <= '0'; creset <='0';
    else
        next_state <= idle; enable<="00"; licz<='0'; drive <= '0'; creset <='0';
    end if;


when read =>
           if (req="100") then
        next_state <= write1; enable <= "00"; licz<='0'; drive <= '1'; creset <='0';
    elsif (req="010") then
        next_state <= compare; enable<="00"; licz<='1'; drive <= '1'; creset <='0';
    elsif (req="001") then
        next_state <= read; enable<="00"; licz<='0'; drive <= '1'; creset <='0';
    else
        next_state <= idle; enable<="00"; licz<='0'; drive <= '1'; creset <='0';
    end if;

when write1 =>
           if (req="100") then
        next_state <= write2; enable <= "01"; licz<='0'; drive <= '0'; creset <='1';
    elsif (req="010") then
        next_state <= write2; enable<="01"; licz<='0'; drive <= '0'; creset <='1';
    elsif (req="001") then
        next_state <= write2; enable<="01"; licz<='0'; drive <= '0'; creset <='1';
    else
        next_state <= write2; enable<="01"; licz<='0'; drive <= '0'; creset <='1';
    end if;

when write2 =>
           if (req="100") then
        next_state <= idle; enable <= "00"; licz<='0'; drive <= '0'; creset <='0';
    elsif (req="010") then
        next_state <= compare; enable<="00"; licz<='1'; drive <= '0'; creset <='0';
    elsif (req="001") then
        next_state <= read; enable<="00"; licz<='0'; drive <= '0'; creset <='0';
    else
        next_state <= idle; enable<="00"; licz<='0'; drive <= '0'; creset <='0';
    end if;

when compare =>
         if (req="100") then
        next_state <= write1; enable <= "00"; licz<='0'; drive <= '0'; creset <='0';
    elsif (req="010") then
        next_state <= compare; enable<="00"; licz<='1'; drive <= '0'; creset <='0';
    elsif (req="001") then
        next_state <= read; enable<="00"; licz<='0'; drive <= '0'; creset <='0';
    else
        next_state <= idle; enable<="00"; licz<='0'; drive <= '0'; creset <='0';
    end if;

end case;
end process;


END ARCHITECTURE z12;
--Kocham Cię, ale nie pokazuj tego na labkach <3