/*
 * I2S_FACTORY.c
 *
 *  Created on: Apr 22, 2021
 *      Author: Christopher
 */

#include <CONSTANTS.h>

#include "stm32h753xx.h"
#include "Opcode.h"

static int I2S1_TxBUFF[4];
static int I2S1_RxBUFF[4];

int * getI2S1_TxBUFF() {

    return I2S1_TxBUFF;
}

int * getI2S1_RxBUFF() {

    return I2S1_RxBUFF;
}

void SET_I2S_GPIO () {

// ! ---- PINS USED
// PA4 = I2S1_WS
// PA5 = I2S1_CK
// PA6 = MISO
// PA7 = MOSI
// PC4 = MCK

// GPIOA & C Clock
RCC->AHB4ENR &= ~((RCC_AHB4ENR_GPIOAEN) |
                  (RCC_AHB4ENR_GPIOCEN));

RCC->AHB4ENR |= (RCC_AHB4ENR_GPIOAEN) |
                (RCC_AHB4ENR_GPIOCEN);


GPIOA->MODER &= ~((GPIO_MODER_MODE4) |
                  (GPIO_MODER_MODE5) |
                  (GPIO_MODER_MODE6) |
                  (GPIO_MODER_MODE7));

GPIOA->MODER |= (GPIO_MODER_MODE4_AF) |
                (GPIO_MODER_MODE5_AF) |
                (GPIO_MODER_MODE6_AF) |
                (GPIO_MODER_MODE7_AF);

GPIOC->MODER &= ~(GPIO_MODER_MODE4);
GPIOC->MODER |=  (GPIO_MODER_MODE4_AF);


GPIOA->OSPEEDR &= ~((GPIO_OSPEEDR_OSPEED4) |
                    (GPIO_OSPEEDR_OSPEED5) |
                    (GPIO_OSPEEDR_OSPEED6) |
                    (GPIO_OSPEEDR_OSPEED7));

GPIOA->OSPEEDR |=   (GPIO_OSPEEDR_OSPEED4_VERY_HIGH_SPEED) |
                    (GPIO_OSPEEDR_OSPEED5_VERY_HIGH_SPEED) |
                    (GPIO_OSPEEDR_OSPEED6_VERY_HIGH_SPEED) |
                    (GPIO_OSPEEDR_OSPEED7_VERY_HIGH_SPEED);

GPIOC->OSPEEDR &= ~((GPIO_OSPEEDR_OSPEED4));
GPIOC->OSPEEDR |=   (GPIO_OSPEEDR_OSPEED4_VERY_HIGH_SPEED);

GPIOA->AFR[0] &= ~((GPIO_AFRL_AFSEL4) |
                   (GPIO_AFRL_AFSEL5) |
                   (GPIO_AFRL_AFSEL6) |
                   (GPIO_AFRL_AFSEL7));

GPIOA->AFR[0] |=   (GPIO_AFRL_AFSEL4_I2S1_WS)   |
                   (GPIO_AFRL_AFSEL5_I2S1_CK)   |
                   (GPIO_AFRL_AFSEL6_I2S1_MISO) |
                   (GPIO_AFRL_AFSEL7_I2S1_MOSI);

GPIOC->AFR[0] &= ~(GPIO_AFRL_AFSEL4);
GPIOC->AFR[0] |=  (GPIO_AFRL_AFSEL4_I2S1_MCK);

}


void SET_I2S_DMA() {

// ENABLE DMA
RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN);
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;

//Setup DMA
DMAMUX1_Channel0->CCR &= ~(DMAMUX_CxCR_DMAREQ_ID);
DMAMUX1_Channel0->CCR |=  (DMAMUX_CxCR_DMAREQ_ID_I2S1_Rx);

DMAMUX1_Channel1->CCR &= ~(DMAMUX_CxCR_DMAREQ_ID);
DMAMUX1_Channel1->CCR |=  (DMAMUX_CxCR_DMAREQ_ID_I2S1_Tx);

DMA1_Stream0->CR &= ~((DMA_SxCR_CT)    |
                      (DMA_SxCR_PL)    |
                      (DMA_SxCR_MSIZE) |
                      (DMA_SxCR_PSIZE) |
                      (DMA_SxCR_MINC)  |
                      (DMA_SxCR_CIRC)  |
                      (DMA_SxCR_DIR)   |
                      (DMA_SxCR_PFCTRL)|
                      (DMA_SxCR_TCIE)  |
                      (DMA_SxCR_HTIE));

DMA1_Stream0->CR |=   (DMA_SxCR_CT_MEM0)           |
                      (DMA_SxCR_PL_VERY_HIGH)      |
                      (DMA_SxCR_MSIZE_32BIT)       |
                      (DMA_SxCR_PSIZE_32BIT)       |
                      (DMA_SxCR_MINC)              |
                      (DMA_SxCR_CIRC)              |
                      (DMA_SxCR_DIR_PERI_TO_MEM)   |
                      (DMA_SxCR_PFCTRL_DMA_FLOW)   |
                      (DMA_SxCR_TCIE)              |
                      (DMA_SxCR_HTIE);

DMA1_Stream1->CR &= ~((DMA_SxCR_CT)    |
                      (DMA_SxCR_PL)    |
                      (DMA_SxCR_MSIZE) |
                      (DMA_SxCR_PSIZE) |
                      (DMA_SxCR_MINC)  |
                      (DMA_SxCR_CIRC)  |
                      (DMA_SxCR_DIR)   |
                      (DMA_SxCR_PFCTRL)|
                      (DMA_SxCR_TCIE)  |
                      (DMA_SxCR_HTIE));

DMA1_Stream1->CR |=   (DMA_SxCR_CT_MEM0)           |
                      (DMA_SxCR_PL_VERY_HIGH)      |
                      (DMA_SxCR_MSIZE_32BIT)       |
                      (DMA_SxCR_PSIZE_32BIT)       |
                      (DMA_SxCR_MINC)              |
                      //(DMA_SxCR_CIRC)              |
                      (DMA_SxCR_DIR_MEM_TO_PERI)   |
                      (DMA_SxCR_PFCTRL_DMA_FLOW);

DMA1_Stream0->NDTR = 4;
DMA1_Stream1->NDTR = 4;

DMA1_Stream0->PAR = (int)&SPI1->RXDR;
DMA1_Stream0->M0AR = (int)I2S1_RxBUFF;

DMA1_Stream1->PAR = (int)&SPI1->TXDR;
DMA1_Stream1->M0AR = (int)I2S1_TxBUFF;
}

void SET_I2S_INTERRUPT () {
    NVIC_SetPriority(DMA1_Stream0_IRQn,0);
    NVIC_EnableIRQ(DMA1_Stream0_IRQn);
}

void INIT_I2S () {

SET_I2S_GPIO();
SET_I2S_DMA();
}