ALU_stricat

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;

entity ALU is
    port(A:in integer;
    B:in integer;
    P:in integer;
    Op: in std_logic_vector(2 downto 0);
    O: out std_logic_vector(3 downto 0));
end ALU;

architecture arhi of ALU is
signal Res:std_logic_vector(3 downto 0);
signal input1:integer;
signal input2:integer;
signal X:std_logic_vector(3 downto 0);
signal Y:std_logic_vector(3 downto 0);

begin
    input1<=A;
    input2<=B;
    X<=conv_std_logic_vector(input1,X'length);
    Y<=conv_std_logic_vector(input2,Y'length);
    process(A,B,Op)
        begin
            case(Op) is
                when "000" => Res <= X + Y;
                when "001" => Res <= X - Y;
                --when "010" => Res <= std_logic_vector(X sll P);
                --when "011" => Res <= std_logic_vector(Y srl P);
                when "100" => Res <= X and Y;
                when "101" => Res <= X or Y;
                when others => Res <= "0000";
            end case;
            O<= Res;
    end process;
end architecture;