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Florii11

ALU_stricat

Mar 30th, 2021
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use ieee.STD_LOGIC_ARITH.all;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5. use IEEE.NUMERIC_STD.all;
  6.  
  7. entity ALU is    
  8.     port(A:in integer;
  9.     B:in integer;
  10.     P:in integer;
  11.     Op: in std_logic_vector(2 downto 0);
  12.     O: out std_logic_vector(3 downto 0));
  13. end ALU;
  14.  
  15. architecture arhi of ALU is
  16. signal Res:std_logic_vector(3 downto 0);
  17. signal input1:integer;
  18. signal input2:integer;
  19. signal X:std_logic_vector(3 downto 0);
  20. signal Y:std_logic_vector(3 downto 0);
  21.  
  22. begin  
  23.     input1<=A;
  24.     input2<=B;
  25.     X<=conv_std_logic_vector(input1,X'length);
  26.     Y<=conv_std_logic_vector(input2,Y'length);
  27.     process(A,B,Op)
  28.         begin
  29.             case(Op) is
  30.                 when "000" => Res <= X + Y;
  31.                 when "001" => Res <= X - Y;
  32.                 --when "010" => Res <= std_logic_vector(X sll P);  
  33.                 --when "011" => Res <= std_logic_vector(Y srl P);
  34.                 when "100" => Res <= X and Y;
  35.                 when "101" => Res <= X or Y;
  36.                 when others => Res <= "0000";
  37.             end case;
  38.             O<= Res;
  39.     end process;
  40. end architecture;
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