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STM32 F3 Timer3 basic PWM setup

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Jul 23rd, 2015
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  1. /*
  2.  * This file is part of the libopencm3 project.
  3.  *
  4.  * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
  5.  * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
  6.  * Modified by Fernando Cortes <fermando.corcam@gmail.com>
  7.  * modified by Guillermo Rivera <memogrg@gmail.com>
  8.  *
  9.  * This library is free software: you can redistribute it and/or modify
  10.  * it under the terms of the GNU Lesser General Public License as published by
  11.  * the Free Software Foundation, either version 3 of the License, or
  12.  * (at your option) any later version.
  13.  *
  14.  * This library is distributed in the hope that it will be useful,
  15.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17.  * GNU Lesser General Public License for more details.
  18.  *
  19.  * You should have received a copy of the GNU Lesser General Public License
  20.  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  21.  */
  22.  
  23. #include <libopencm3/stm32/rcc.h>
  24. #include <libopencm3/stm32/gpio.h>
  25. #include <libopencm3/stm32/timer.h>
  26. #include <libopencm3/stm32/flash.h>
  27.  
  28. /*
  29.  A basic routine to adjust system clock settings to get SYSCLK
  30.  to 64 MHz, and have AHB buses at 64 MHz, and APB Bus at 32 MHz (its max speed)
  31.  Copied from:
  32.  https://github.com/libopencm3/libopencm3-examples/blob/master/examples/stm32/f3/stm32f3-discovery/adc/adc.c
  33.  */
  34.  
  35. static void set_system_clock(void)
  36. {
  37.     rcc_clock_setup_hsi(&hsi_8mhz[CLOCK_64MHZ]);
  38. }
  39.  
  40. static void setup_timer3_pwm(void)
  41. {
  42.     rcc_periph_clock_enable(RCC_GPIOC);
  43.     gpio_set_output_options(GPIOC, GPIO_OTYPE_PP,
  44.                         GPIO_OSPEED_50MHZ, GPIO8 | GPIO9);
  45.     gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8 | GPIO9);
  46.     gpio_set_af(GPIOC, GPIO_AF2, GPIO8 | GPIO9);
  47.  
  48.     timer_reset(TIM3);
  49.     rcc_periph_clock_enable(RCC_TIM3);
  50.  
  51.     timer_continuous_mode(TIM3);
  52.  
  53.     timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1,
  54.                TIM_CR1_DIR_UP);
  55.     timer_set_oc_mode(TIM3, TIM_OC3, TIM_OCM_PWM1);
  56.     timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1);
  57.  
  58.     timer_set_period(TIM3, 32000);
  59.  
  60.     timer_enable_preload(TIM3);
  61.     timer_enable_oc_preload(TIM3, TIM_OC3);
  62.     timer_enable_oc_preload(TIM3, TIM_OC4);
  63.     timer_set_oc_polarity_high(TIM3, TIM_OC3);
  64.     timer_enable_oc_output(TIM3, TIM_OC3);
  65.     timer_enable_oc_output(TIM3, TIM_OC4);
  66.     timer_enable_counter(TIM3);
  67.  
  68.     timer_enable_update_event(TIM3);
  69.     timer_generate_event(TIM3, TIM_EGR_UG);
  70. }
  71.  
  72.  
  73. int main(void)
  74. {
  75.     set_system_clock();
  76.     setup_timer3_pwm();
  77.  
  78.     while (1)
  79.     {
  80.         if(timer_get_flag(TIM3, TIM_SR_UIF))
  81.         {
  82.             timer_clear_flag(TIM3, TIM_SR_UIF);
  83.             timer_set_oc_value(TIM3, TIM_OC3, 16000);
  84.             timer_set_oc_value(TIM3, TIM_OC4, 24000);
  85.         }
  86.     }
  87.  
  88.     return 0;
  89. }
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