Advertisement
Guest User

Untitled

a guest
Oct 16th, 2019
145
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1.             # LiteDRAM port ------------------------------------------------------------------------
  2.             port = self.sdram.crossbar.get_port()
  3.             port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
  4.  
  5.             # Parameters ---------------------------------------------------------------------------
  6.             main_ram_size = 2**(geom_settings.bankbits +
  7.                                 geom_settings.rowbits +
  8.                                 geom_settings.colbits)*phy.settings.databits//8
  9.             main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
  10.  
  11.             # SoC <--> L2 Cache Wishbone interface -------------------------------------------------
  12.             # FIXME: we do this here just so that we get MAIN_RAM_BASE in the generated .h file!!!
  13.             # FIXME: we don't actually *use* the resulting self._wb_sdram interface!!!
  14.             wb_sdram = wishbone.Interface()
  15.             self.add_wb_sdram_if(wb_sdram)
  16.             self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
  17.  
  18.             # LiteDRAM AXI port --------------------------------------------------------------------
  19.             # FIXME: figure out offset here:vvvvvvvvvvvvvvvvvvvvvv
  20.             axi2native = LiteDRAMAXI2Native(self.cpu.mem_axi, port)
  21.             self.submodules += axi2native
Advertisement
Advertisement
Advertisement
RAW Paste Data Copied
Advertisement