# LiteDRAM port ------------------------------------------------------------------------
            port = self.sdram.crossbar.get_port()
            port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2

            # Parameters ---------------------------------------------------------------------------
            main_ram_size = 2**(geom_settings.bankbits +
                                geom_settings.rowbits +
                                geom_settings.colbits)*phy.settings.databits//8
            main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now

            # SoC <--> L2 Cache Wishbone interface -------------------------------------------------
            # FIXME: we do this here just so that we get MAIN_RAM_BASE in the generated .h file!!!
            # FIXME: we don't actually *use* the resulting self._wb_sdram interface!!!
            wb_sdram = wishbone.Interface()
            self.add_wb_sdram_if(wb_sdram)
            self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)

            # LiteDRAM AXI port --------------------------------------------------------------------
            # FIXME: figure out offset here:vvvvvvvvvvvvvvvvvvvvvv
            axi2native = LiteDRAMAXI2Native(self.cpu.mem_axi, port)
            self.submodules += axi2native