library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
    port(
        clk             : in std_logic;
        rst             : in std_logic;
        load            : in std_logic;
        ena             : in std_logic;
        data_bus    : in std_logic_vector(3 downto 0);
        value       : out std_logic_vector(3 downto 0)
    );
end test2;

architecture data_flow of test2 is
    signal cnt_reg, cnt_next : unsigned(3 downto 0);
begin
        process (clk, rst)
            begin
                if (rst = '1') then
                    cnt_reg <= (others => '0');
                elsif (rising_edge(clk)) then
                    cnt_reg <= cnt_next;
                end if;
        end process;

        cnt_next <= unsigned(data_bus) when load = '1' else
                        cnt_reg + 1 when ena = '1' else
                        cnt_reg;


        value <= std_logic_vector(cnt_reg);
end data_flow;