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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 12:29:38 04/24/2019
- -- Design Name:
- -- Module Name: sound_3_3 - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity sound_3_3 is
- Port ( CLK : in STD_LOGIC;
- SOUND : out STD_LOGIC);
- end sound_3_3;
- architecture Behavioral of sound_3_3 is
- signal counter : STD_LOGIC_VECTOR (23 downto 0);
- signal tym : STD_LOGIC;
- signal nr_stanu : STD_LOGIC_VECTOR (3 downto 0); JEŻELI LICZBA STANÓW SIĘ NIE ZMIEŚCI, TUTAJ TEŻ TRZEBA ZMIENIĆ
- begin ILOŚĆ BITÓW
- process(CLK)
- begin
- if rising_edge(CLK) then
- counter<=counter+1;
- if(counter=6250000) then TU ZMIENIACIE CZĘSTOTLIWOŚĆ (50000000/CZĘSTOTLIWOŚĆ/2)
- counter<="000000000000000000000000";
- tym<=not tym;
- end if;
- end if;
- end process;
- process(tym)
- begin
- if rising_edge(tym) then
- nr_stanu<=nr_stanu+1;
- if nr_stanu=9 then TU TRZEBA ZMIENIĆ ODPOWIEDNIO NUMER STANU
- nr_stanu<="0000";
- end if;
- end if;
- end process;
- with nr_stanu select TU DOPISUJECIE STANY I TAM GDZIE JEST WYSOKI TO JEDEN A NISKI TO ZERO
- SOUND <='1' when "0000",
- '0' when "0001",
- '1' when "0010",
- '1' when "0011",
- '0' when "0100",
- '1' when "0101",
- '1' when "0110",
- '1' when "0111",
- '0' when "1000",
- '0' when "1001",
- '0' when others;
- end Behavioral;
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