Berd Exam 2

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity inverse is
        Port(
            a: in std_logic;
            aprime: out std_logic
        );
End inverse;

architecture a_inv of inverse is
begin
    aprime <= not a;
end a_inv;

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity mux is
    port (
        sig1,sig2,sel: in std_logic;
        output: out std_logic
    );
end mux;
architecture a_mux of mux is
begin
    output <= sig1 when sel = '0' else
                sig2 when sel = '1';
end a_mux;

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

Entity toplevel is
    port(
        a,b, sel: in std_logic;
        mux_out: out std_logic
    );
end;

architecture a_top of toplevel is
signal o1,o2: std_logic;
component inverse is
        Port(
            a: in std_logic;
            aprime: out std_logic
        );
    End component inverse;
Component mux is
    port (
            sig1,sig2,sel: in std_logic;
            output: out std_logic
        );
end component mux;
begin

    I1: inverse port map(
        a =>a,
        aprime=>o1
    );
    I2: inverse port map(
        a =>o1,
        aprime=>o2
    );
    M1: mux port map(
        sig1=>o2,
        sig2=>b,
        sel=>sel,
        output=>mux_out
    );
end a_top;